基于FPGA的TTCAN总线控制器的设计与验证  

Design and verification of TTCAN bus controller based on FPGA

作　　者：曹燕 许高斌 周东升 马渊明 冯建国 CAO Yan;XU Gaobin;ZHOU Dongsheng;MA Yuanming;FENG Jianguo(School of Microelectronics,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]合肥工业大学微电子学院,安徽合肥230601

出　　处：《合肥工业大学学报(自然科学版)》2025年第1期50-58,共9页Journal of Hefei University of Technology:Natural Science

基　　金：国家重点研发计划资助项目(2022YFB3205903);安徽省发改委研发创新资助项目(JZ2021AFKJ0050)。

摘　　要：为了提高控制器局域网络(controller area network,CAN)通信的实时性,文章基于时间触发CAN(time-triggered CAN,TTCAN)协议,采用verilog硬件描述语言设计实现TTCAN总线控制器。该控制器可在经典CAN模式与TTCAN模式之间进行切换,同时兼容可变速率CAN(CAN with flexible data rate,CAN FD)协议下的高速通信。实验结果证明,相较于经典CAN总线控制器,该TTCAN总线控制器能够减少在高总线负载率下周期性报文的发送延时,在全波特率范围内且总线负载率大于等于60%的情况下,能够减少75%以上的CAN报文发送延时。To improve the real-time communication performance of the controller area network(CAN),this paper designed a time-triggered CAN(TTCAN)bus controller based on the TTCAN protocol using the verilog hardware description language.The controller can switch between classical CAN mode and TTCAN mode and is compatible with high-speed communication under the CAN with flexible data rate(CAN FD)protocol.Experimental results show that the TTCAN bus controller can reduce the transmission delay of periodic messages under high bus load rates compared with the classical CAN bus controller.Within the full baud rate range,the TTCAN bus controller can reduce the delay of CAN message transmission by more than 75%when the bus load rate is greater than or equal to 60%.

关 键 词：控制器局域网络(CAN) 时间触发 可变速率控制器局域网络(CAN FD) 总线负载率 周期性报文 

分 类 号：TN791[电子电信—电路与系统]