一种高线性度高精度的ZOOM模数转换器设计  

Design of ZOOM ADC with High Linearity and High Resolution

作　　者：刘才盛 冯忱晖 LIU Caisheng;FENG Chenhui(College of Physics and Information Engineering,Fuzhou University,Fuzhou 350108,China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《仪表技术》2025年第1期30-34,共5页Instrumentation Technology

摘　　要：高线性度、高精度的模数转换器(ADC)在传感器应用中具有重要作用。设计了一款针对低频信号检测的ZOOM ADC,其带宽为1 kHz。该ADC架构结合了5 bit的SAR ADC和12 bit的二阶增量型Sigma Delta ADC,利用增量型Sigma Delta ADC的周期性复位特征及采样前端引入的采样保持模块,提升了整体ADC的线性度。在SAR ADC设计中,采用了基于共模电压的电容开关时序的数模转换器(DAC)阵列;在增量型Sigma Delta ADC设计中,采用高能效电流饥饿型运算放大器进行积分器设计,有效降低了系统功耗。采用SMIC 40 nm工艺,系统时钟为256 kHz, 1 kHz带宽下的信噪比为93.2 dB、有效位数为15.19 bit。等间隔输入模拟直流信号,ZOOM ADC的输入输出曲线呈现出良好的线性度。High linearity and high precision analog⁃to⁃digital converters(ADCs)play an important role in sensor applications.A ZOOM ADC is designed for low⁃frequency signal detection with a bandwidth of 1 kHz.This ADC architecture combines a 5⁃bit SAR ADC and a 12 bit second⁃order incremental Sigma Delta ADC,utilizing the periodic reset feature of the incremental Sigma Delta ADC and the sample⁃and⁃hold module introduced by the sampling front⁃end to improve the overall linearity of the ADC.In the design of SAR ADC,a digital to analog converter(DAC)array based on common mode voltage and capacitor switching timing is adopted.In the incremental Sigma Delta ADC design,a high⁃efficiency current hungry operational amplifier is used for integrator design,effectively reducing system power consump⁃tion.Using SMIC 40 nm process,the system clock is 256 kHz,the signal⁃to⁃noise ratio at 1 kHz bandwidth is 93.2 dB,and the effective bit count is 15.19 bits.The input⁃output curve of the ZOOM ADC shows good linearity when inputting analog DC signals at equal intervals.

关 键 词：模数转换器 高线性度 共模电压 电流饥饿型 

分 类 号：TN792[电子电信—电路与系统]