NA-ROB:基于RISC-V超标量处理器的改进  

NA-ROB:improvement based on RISC-V superscalar processors

作　　者：景超霞 刘杰 李洪奎 刘红海[1] Jing Chaoxia;Liu Jie;Li Hongkui;Liu Honghai(School of Information Engineering,Huzhou University,Huzhou Zhejiang 313000,China)

机构地区：[1]湖州师范学院信息工程学院,浙江湖州313000

出　　处：《计算机应用研究》2025年第2期519-522,共4页Application Research of Computers

基　　金：湖州市公益重点资助项目(2019GZ10);浙江省本科高校省级线下一流本科课程(浙教办函[2020]77号);浙江省重点实验室资助项目(2020E10017)。

摘　　要：重排序缓存(ROB)是超标量处理器中的重要模块,用于确保乱序执行的指令能够正确地完成和提交。然而,在大规模超标量处理器中,存在ROB阻塞以及ROB容量有限的问题。为了解决上述问题并提高处理器性能,提出了零寄存器分配策略,通过将没有目的寄存器的指令单独存储来避免占用ROB表项。同时,引入容量可动态调整的缓存结构(AROB),将长延时指令与普通指令分别存储在ROB和AROB中,以降低长延时指令导致的阻塞。改进后的超标量处理器被命名为NA-ROB,经过SPEC 2006基准测试程序的实验评估,结果表明,NA-ROB超标量处理器相比于传统的ROB超标量处理器,平均IPC提升了66%,同时ROB的阻塞概率降低了48%。因此,所提出的改进方法显著提升了处理器的整体性能和效率。The reorder buffer(ROB)is a critical module in superscalar processors,ensuring that instructions executed out-of-order can be correctly completed and committed.However,in large-scale superscalar processors,issues such as ROB blocking and limited ROB capacity arise.To address these issues and enhance processor performance,this paper proposed a zero-register allocation strategy,which stored instructions without destination registers separately to avoid occupying ROB entries.Additio-nally,it introduced a dynamically adjustable cache structure(AROB),storing long-latency instructions and regular instructions separately in the ROB and AROB,respectively,to reduce blocking caused by long-latency instructions.The improved superscalar processor,named NA-ROB,was evaluated using the SPEC 2006 benchmark suite.Experimental results show that the NA-ROB superscalar processor achieves a 66%average IPC improvement compared to traditional ROB superscalar processors,while reducing the probability of ROB blocking by 48%.Thus,the proposed improvements significantly enhance the overall performance and efficiency of the processor.

关 键 词：RISC-V指令集 超标量处理器 ROB AROB 零寄存器分配策略 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]