Software-defined process-near-memory architecture using 3D hybrid bonding integration  

作　　者：Anlin XU Chenchen DENG Jianfeng ZHU Yao WANG Shaojun WEI Leibo LIU 

机构地区：[1]School of Integrated Circuits,Tsinghua University,Beijing 100084,China [2]Beijing Institution of Tracking and Communication Technology,Beijing 100094,China [3]Beijing National Research Center for Information Science and Technology,Tsinghua University,Beijing 100084,China

出　　处：《Science China(Information Sciences)》2025年第1期363-375,共13页中国科学(信息科学)(英文版)

基　　金：supported by National Key R&D Program of China(Grant No.2021YFB3100903);Beijing Superstring Academy of Memory Technology;National Natural Science Foundation of China(Grant Nos.61834002,62104129,2022-XXXX-ZD-005-00).

摘　　要：With the unprecedented explosive growing amount of global data,the development of computing chips,which encounter bottlenecks such as power wall and memory wall,cannot satisfy the demanding requirement.This work proposes a software-defined process-near-memory(SDPNM)computing architecture implemented using 3D hybrid bonding integration.The software-defined chip architecture,featuring spatial computations and dynamic reconfiguration,innovates in a top-down manner to achieve high energy efficiency while maintaining flexibility after fabrication.The process-near-memory integration further advances the SDNPM chip in a bottom-up way to reduce the energy consumption of data movement while improving the bandwidth.Utilizing a relatively mature fabrication and bonding process can result in feasible solutions for both data-intensive and compute-intensive applications including digital signal processing and artificial intelligence.The logic die is fabricated in the SMIC 40 nm process and the DRAM die is fabricated in the PSMC 25 nm process.The hybrid bonding is implemented by XMC.The experimental results show that the energy efficiency of the proposed SDPNM chip is 33.1×better than the state-of-the-art FPGA ranging from 8.2×to 104.1×.

关 键 词：software-defined chips process near memory energy efficiency dynamic reconfiguration domain specific 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN40[自动化与计算机技术—计算机科学与技术]