基于动态偏置误差放大器的超低功耗LDO设计  

Design of ultra-low power LDO based on dynamic bias error amplifier

作　　者：袁小龙 吴巍 王俊峰 YUAN Xiaolong;WU Wei;WANG Junfeng(College of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,China;Nanjing Yudu Communication Technology Co.,Ltd.,Nanjing 210046,China)

机构地区：[1]南京邮电大学集成电路科学与工程学院,江苏南京210023 [2]南京宇都通讯科技有限公司,江苏南京210046

出　　处：《电子元件与材料》2024年第12期1502-1508,共7页Electronic Components And Materials

摘　　要：为了满足便携式设备对低功耗的需求,同时解决低功耗下低压差线性稳压器(LDO)瞬态响应差的问题,设计了一款带有动态偏置误差放大器的超低功耗无片外电容LDO。采用了自适应偏置电路为误差放大器提供偏置电流,同时结合动态偏置,既能降低轻载时的静态功耗,又能提高瞬态响应能力;采用了亚阈值CMOS基准,相比于传统带隙基准,面积更小,功耗更低。电路基于SMIC 55 nm CMOS工艺设计,实现了工作电压范围1.4~2 V,输出电压1.1 V,最大输出电流100 mA。仿真表明,所设计的LDO最小静态电流仅为580 nA,负载在1~100 mA范围以1μs跳变时,过冲和下冲电压分别为123 mV和113 mV,稳定恢复时间分别为4.1μs和3.5μs。该LDO适用于需要长时间续航的小型设备。In order to meet the demand for low power consumption in portable electronic devices and address the issue of poor transient response of low dropout linear regulators(LDO)under low power consumption,an ultra-low-power capacitor-free LDO was designed.An adaptive bias circuit was used to provide bias current to the error amplifier and combined with dynamic biasing in order to reduce static power consumption at light loads and improve transient response;A sub-threshold CMOS reference was used,resulting in a smaller area and lower power consumption than conventional bandgap references.The circuit was designed based on SMIC 55 nm CMOS process and an operating voltage range of 1.4-2 V,an output voltage of 1.1 V and a maximum output current of 100 mA were achieved.Simulation results show that the designed LDO has a minimum quiescent current of just 580 nA.With loads jumping in 1μs from 1 mA to 100 mA,the overshoot and undershoot voltages are 123 mV and 113 mV,respectively,with stable recovery times of 4.1μs and 3.5μs.This LDO is suitable for small devices that require long term battery life.

关 键 词：动态偏置误差放大器 超低功耗 无片外电容LDO 自适应偏置 CMOS基准 

分 类 号：TN432[电子电信—微电子学与固体电子学]