基于Fan-out技术的三维堆叠封装  

3D Stacking Package Based on Fan-out Wafer Level Packing Technology

作　　者：姚昕 王斌 张荣臻 YAO Xin;WANG Bin;ZHANG Rongzhen(Wuxi Zhongwei High-Tech Electronics Co.,Ltd.,Wuxi 214000,China)

机构地区：[1]无锡中微高科电子有限公司,江苏无锡214000

出　　处：《电子产品可靠性与环境试验》2024年第6期100-103,共4页Electronic Product Reliability and Environmental Testing

摘　　要：基于扇出型晶圆级封装工艺(Fan-out工艺)技术的三维集成已成为实现电子系统元器件高集成度、小型化和低成本应用的有效途径。设计了一种基于Fan-out技术的三维堆叠封装DDR3存储模块,其相比于独立10片DDR3芯片在系统板上节省75%的空间。通过对多层堆叠存储模块的系统需求与方案设计分析、电设计与仿真优化研究确定电路的结构与布线设计,最终研制生产的产品接触失效测试正常,功能码正确测试通过,电路各项指标均可满足系统的设计要求,验证了本设计的合理性。The three-dimensional integration based on Fan-out wafer-level packaging process technology has become an effective way to electronic system components to achieve high integration,miniaturization and low-cost applications.A 3D stacking package of DDR3 storage module based on Fan-out technology is designed,which saves 75%of space on the system board compared with the 10 independent DDR3 chips.Through the study of the system requirements,scheme design analysis,electronic design and simulation optimization of the multi-layer stack storage modules,the structure and wiring design of the circuit are determined,the contact failure test of the final products developed and produced is normal,the function code is passed correctly,all indicators of the circuit can meet the design requirements of the system,which verifies the rationality of this design.

关 键 词：扇出型晶圆级封装工艺 三维堆叠封装 DDR3存储模块 高集成度 

分 类 号：TN305.94[电子电信—物理电子学]