一种65 nm CMOS毫米波宽带低噪声放大器设计  

Design of a 65 nm CMOS millimeter wave wideband Low-Noise Amplifier

作　　者：诸恒俊 张长春[1] 王静[1] 张翼[1] ZHU Hengjun;ZHANG Changchun;WANG Jing;ZHANG Yi(College of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,China)

机构地区：[1]南京邮电大学集成电路科学与工程学院,江苏南京210023

出　　处：《电子设计工程》2025年第4期1-5,共5页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(62174090);毫米波国家重点实验室开放课题(K202325)。

摘　　要：基于65 nm CMOS工艺设计了一款适用于5G毫米波相控阵接收机的宽带低噪声放大器(LNA)。该LNA主要由两级共源共栅(Cascode)放大器和输入、输出及级间耦合变压器构成。其中,第一级Cascode放大器采用栅-源间变压器磁耦跨导增强技术以提高增益;第二级Cascode放大器采用交叉耦合中和电容技术以扩展带宽;输入、输出及级间耦合变压器用以实现宽带阻抗匹配及提高增益平坦度等。仿真结果表明,所设计的LNA在24~29.5 GHz频带内能够取得高达22.3 dB的电压增益,优于±1 dB的增益平坦度以及低达4.4 dB的噪声系数,核心版图面积为683μm×147μm。A broadband Low-Noise Amplifier(LNA)for 5G millimeter wave phased-array receivers has been designed based on a 65 nm CMOS process.The LNA mainly consists of two stages of common-source,common-gate(Cascode)amplifiers and input,output,and inter-stage coupling transformers.Among them,the first stage Cascode amplifier adopts the gate-source transformer magnetic coupling transconductance enhancement technique to improve the gain;the second stage Cascode amplifier adopts the cross-coupling neutralization capacitance technique to extend the bandwidth;the input,output and inter-stage coupling transformers are used to realize the broadband impedance matching and improve the gain flatness.Simulation results show that the designed LNA can achieve a voltage gain of up to 22.3 dB,a gain flatness better than±1 dB,and a noise figure as low as 4.4 dB in the 24~29.5 GHz band.The core layout area is 683μm×147μm.

关 键 词：毫米波 低噪声放大器 增益平坦度 变压器宽带匹配 中和电容 

分 类 号：TN432[电子电信—微电子学与固体电子学]