基于动态时序裕量压缩的高性能处理器设计  

High-performance processor design based on dynamic timing slack exploitation

作　　者：连子涵 何卫锋[1] LIAN Zihan;HE Weifeng(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《计算机工程与科学》2025年第2期219-227,共9页Computer Engineering & Science

摘　　要：传统的同步电路设计方法根据静态时序分析得到的关键路径确定工作频率,但是关键路径并不是每个周期都会被激发,在关键路径和实际激发路径之间存在动态时序裕量。为此,提出了一种基于指令级时序裕量压缩的高性能处理器设计方法,旨在最大化压缩动态时序裕量从而获得性能提升。搭建了时序分析平台自动化获取指令时序;设计了一种时序编码策略,在不增加硬件开销的基础上将时序信息通过指令编码传递到硬件,并在硬件层设计了时序译码及仲裁电路,根据指令时序编码相应调节时钟周期,从而实现了指令级动态时序裕量压缩。在一款基于RISC-V指令集的超标量处理器上完成所提方法的仿真验证,结果表明,相比传统设计方法,通过该方法最高可获得31%的性能提升。Conventional synchronous circuit design methods determine the operating frequency based on the critical path identified through static timing analysis.However,the critical path is not excited every cycle,leading to dynamic timing slack between the critical path and the actual activated path.Therefore,a high-performance processor design method based on instruction-level timing slack exploitation is proposed,aiming to maximize the exploitation of dynamic timing slack for performance improvement.An automated timing analysis platform is built to obtain instruction timing.A timing encoding strategy is designed to transmit timing information to the hardware through instruction encoding without increasing hardware overhead.Additionally,a timing decoding and arbitration circuit is designed at the hardware level to adjust the clock cycle accordingly based on the instruction timing encoding,thereby achieving instruction-level dynamic timing slack exploitation.Simulation verification of the proposed method is conducted on a superscalar processor based on the RISC-V instruction set.The results show that,compared to traditional design methods,this method can achieve a maximum performance improvement of 31%.

关 键 词：时序裕量 高性能 处理器 RISC-V 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]