基于公共项共享的改进双三次插值算法电路研究  

Research on lmproved Bicubie Interpolation Algorithm Circuit Based on Common Factor Sharing

作　　者：完海 张肖强 杨帆 郑辛星[2] WAN Hai;ZHANG Xiaoqiang;YANG Fan;ZHENG Xinxing(School of Electrical Engineering(School of Integrated Circuits),Anhui Polytechnic University,Anhui Wuhu 241000,China;School of Information and Artificial Intelligence,Wuhu Institute of Technology,Anhui Wuhu 241000,China)

机构地区：[1]安徽工程大学电气工程学院(集成电路学院),安徽芜湖241000 [2]芜湖职业技术学院信息与人工智能学院,安徽芜湖241000

出　　处：《重庆工商大学学报(自然科学版)》2025年第1期112-122,共11页Journal of Chongqing Technology and Business University:Natural Science Edition

基　　金：安徽省自然科学基金面上项目(1908085MF179);安徽省高校自然科学研究重点项目(KJ2019A0983);安徽省教育厅高校优秀科研创新团队项目(2022AH010059);芜湖职业技术学院优秀青年拔尖人才项目;芜湖职业技术学院校级科学研究重点项目(WZYZRZD202302).

摘　　要：目的针对传统双三次插值缩放算法硬件资源消耗大、计算速度相对较慢的问题,提出一种利用公共项共享的改进双三次插值算法硬件电路优化方法。方法该方法涉及构建双三次插值的插值系数计算公式,采用公因式消除法简化公式,目的是提取插值系数计算中的公共成分和中间插值系数;随后,在硬件电路实施过程中,将这些公共成分合并起来,进行综合计算;最终,通过对中间插值系数的表述和共享组件的整合,构建出一个优化的双三次插值电路。结果理论分析表明:乘法器数量从36个减少到20个,从而降低了硬件资源消耗;所构建的双三次插值电路使用硬件描述语言,并使用AMD Xilinx的Vivado开发工具进行综合。实验结果表明:优化后的双三次插值电路在基础层面上减少了8%的LUT(查找表)、2%的LUTRAM和14%的DSP(数字信号处理器)资源。结论事实证明:与现有优化技术相比,基于公因子共享的双三次插值算法优化方法能更有效地减少硬件电路资源消耗,同时保持图像缩放质量。Objective Aiming at the issues of large hardware resource consumption and the relatively slow calculation speed of traditional bicubic interpolation scaling algorithms,this study proposed a method to optimize hardware circuits using an improved bicubic interpolation algorithm based on common factor sharing.Methods This method involves constructing interpolation coefficient calculation formulas for bicubic interpolation.The common factor elimination method is employed to simplify the formulas,aiming to extract common components and intermediate interpolation coefficients in the calculation of interpolation coefficients.Subsequently,in the process of implementing hardware circuits,these common components are merged for comprehensive calculation.Finally,by representing the intermediate interpolation coeficients and integrating shared components,an optimized bicubic interpolation circuit is constructed.Results Theoretical analysis shows that the number of multipliers is reduced from 36 to 20,thereby reducing hardware resource consumption.The constructed bicubic interpolation circuit is described using hardware description language and synthesized using AMD Xilinx's Vivado development tool.Experimental results demonstrate that the optimized bicubic interpolation circuit reduces 8% of the LUTs(lookup tables),2% of the LUTRAMs,and 14%of the DSP(digital signal processor)resources at the basic level.Conclusion The study proves that compared with existing optimization techniques,the optimization method based on common factor sharing for bicubic interpolation algorithms can more effectively reduce hardware circuit resource consumption while maintaining image scaling quality.

关 键 词：双三次插值缩放算法 公共项共享 硬件电路优化 插值系数 

分 类 号：TP751[自动化与计算机技术—检测技术与自动化装置]