高精度流水线逐次逼近混合型模数转换器设计  

High-precision Pipelined-successive Approximation Register Hybrid Analog-to-digital Converter Design

作　　者：叶茂 白春阳[1,2] 郑肖肖 赵毅强 YE Mao;BAI Chunyang;ZHENG Xiaoxiao;ZHAO Yiqiang(School of Microelectronics,Tianjin University,Tianjin 300072,China;Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学微电子学院,天津300072 [2]天津大学天津市成像与感知微电子技术重点实验室,天津300072

出　　处：《湖南大学学报(自然科学版)》2025年第2期140-150,共11页Journal of Hunan University:Natural Sciences

基　　金：国家重点研发计划资助项目(2023YFB4402800)。

摘　　要：为满足数字X射线系统中光电二极管阵列读出电路对平均性能优越的模数转换器(analog-to-digital converter,ADC)的要求,设计一款高精度流水线逐次逼近混合型模数转换器.采用带有预放大级的增益增强型放大器结构,实现了高能效运放设计.使用最低有效位(least significant bit,LSB)平均抗噪声方法,简化第二级比较器结构,有效降低了系统功耗.运用基于延迟锁相环(delay-locked loop,DLL)反馈环路实现比较器时钟自调节,提高了异步时序鲁棒性.基于0.18µm EPI BCD工艺完成对ADC电路设计、版图绘制和后仿真验证.在5.0 V供电电压、5 MS/s采样率的条件下,有效位数ENOB为15.61 bit,信噪失真比SNDR为95.73 dB,非杂散动态范围SFDR为110.72 dB.To meet the requirements of the readout circuit of the photodiode array in the digital X-ray system for an analog-to-digital converter(ADC)with superior average performance,a high-precision pipelinedsuccessive approximation register analog-to-digital converter is designed.It features a gain-enhanced amplifier structure with a pre-amplification stage to realize the high efficiency amplifier.The use of the least significant bit(LSB)averaging noise-resistant method simplifies the structure of the second-stage comparator,effectively reducing overall system power consumption.The self-adjusted comparator clock is also realized using a feedback loop based on a delay-locked loop(DLL),enhancing asynchronous timing robustness.The ADC circuit design,layout,and post-simulation verification were completed using the 0.18µm EPI BCD process.Under 5.0 V supply voltage and 5 MS/s sampling rate conditions,the ADC achieves an ENOB of 15.61 bits,an SNDR of 95.73 dB,and an SFDR of 110.72 dB.

关 键 词：集成电路 模数转换器 LSB平均抗噪声 DLL时钟自调节环路 高能效运放 

分 类 号：TN792[电子电信—电路与系统]