基于RS编译码器的NAND FLASH纠错系统设计与实现  

Design and Implementation of NAND FLASH Error Correction System Based on RS Codec

作　　者：董天 张会新[1] DONG Tian;ZHANG Huixin(Key Laboratory of Micro/nano Devices and Systems,Ministry of Education,North University of China,Taiyuan 030051)

机构地区：[1]中北大学微纳器件与系统教育部重点实验室,太原030051

出　　处：《舰船电子工程》2024年第12期121-125,140,共6页Ship Electronic Engineering

基　　金：国家自然科学基金项目(编号:51705475)资助。

摘　　要：针对某国产型号NAND FLASH在数据读写过程中因外部噪声干扰而引入误码的严峻挑战,文章研究并设计了一种基于RS(Reed Solomon)编译码核的NAND FLASH纠错方案,旨在提高数据传输的可靠性和准确性。设计采用国微SM29F128G08SDM型号128 GB大容量存储芯片,基于Xilinx FPGA平台ISE14.7开发环境,调用并控制缩短码RS(128,120)IP核进行数据编译码功能仿真和实测验证。实验结果表明,在牺牲6.25%的带宽和FLASH内存开销的前提下,最多可实现对突发性连续4个码元进行纠错的功能,极大提高了存储芯片进行数据读写操作的可靠性与准确度,目前已经成功应用于某国产化航天测控项目领域。In order to improve the reliability and accuracy of data transmission,this paper studies and designs a NAND FLASH error correction scheme based on RS(Reed Solomon)encoding and decoding kernel.Based on Xilinx FPGA platform ISE14.7 development environment,128 GB large capacity memory chip of SM29F128G08SDM is used in the design.The shortened code RS(128,120)IP core is invoked and controlled to simulate and verify the data encoding and decoding function.The experi⁃mental results show that under the premise of sacrificing 6.25%bandwidth and FLASH memory overhead,the error correction func⁃tion can be realized for up to 4 sudden consecutive symbols,which greatly improves the reliability and accuracy of data read and write operations of memory chips.

关 键 词：NAND FLASH 误码率 RS编译码 纠错机制 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]