MIPS处理器核及其定制化AXI总线设计  

MIPS processor core and customized AXI bus design

作　　者：周艳娇 贾艳双 杜军[1] ZHOU Yanjiao;JIA Yanshuang;DU Jun(School of Computer Science and Information Engineering,Harbin Normal University,Harbin 150025,China)

机构地区：[1]哈尔滨师范大学计算机科学与信息工程学院,哈尔滨150025

出　　处：《集成电路与嵌入式系统》2025年第3期33-40,共8页Integrated Circuits and Embedded Systems

摘　　要：针对使用现成AXI接口IP核存在资源占用较大、可定制性差等问题,提出一种分阶段自主设计、添加AXI总线的方式,为设计好的MIPS处理器核增加AXI总线的支持。设计使用Verilog HDL编写RTL代码,在Vivado仿真环境下验证了处理器的总体逻辑功能,并将比特流文件下载至FPGA开发板中进行原型验证,得到资源利用率及时序情况。最终使用DC(Design Compiler)工具对处理器进行综合,得到处理器的总体面积和功耗。验证结果表明,自主设计、添加AXI总线相较于直接添加AXI接口IP核所消耗的资源和面积更小,且可以确保在处理器核心架构不变的情况下添加总线,大大降低了将处理器核中原有接口直接更改为AXI总线接口的难度,既减轻了集成的复杂性又兼顾高度定制化,以满足特定的系统需求和性能要求。To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores,a phased,self-designed approach is proposed to add AXI bus support to a designed MIPS processor core.The design is implemented using Verilog HDL for writing RTL code.The overall logic functionality of the processor was verified in the Vivado simulation environment,and the bitstream file was downloaded to the FPGA development board for prototype verification to obtain utilization and timing.Finally,the processor is synthesized using the Design Compiler(DC)tool,and the overall area and power consumption of the processor are evaluated.The verification results indicate that the self-designed AXI bus consumes fewer resources and occupies less area compared to directly using an AXI interface IP core.Furthermore,this approach ensures that the AXI bus is added without changing the processor core architecture,significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface.It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.

关 键 词：AXI IP核 MIPS 处理器核 六级流水线 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]