基于FPGA的全数字正弦波锁相环设计  

Design of an All-Digital Sine Wave Phase-Locked Loop Based on FPGA

作　　者：徐晓康 林德荣 邱长青 Xu Xiaokang;Lin Derong;Qiu Changqing(National Key Laboratory of Electromagnetic Energy,Wuhan 430064,China)

机构地区：[1]电磁能技术全国重点实验室,武汉430064

出　　处：《船电技术》2025年第3期47-49,52,共4页Marine Electric & Electronic Engineering

摘　　要：文章阐述了一种基于FPGA的全数字正弦波锁相环设计。该设计包含乘法器、FIR滤波器、数字PI控制器、数控振荡器等组件。文中详细推导了锁相环各组件的数学模型,用于指导Verilog模块实现与控制参数选取,最后在Vivado 2023.2中仿真验证了此锁相环在1kHz至1.1kHz频率区间内具有良好的锁相性能。The article describes a fully digital sine wave phase-locked loop(ADPLL)design based on FPGA.This design includes components such as a multiplier,FIR filter,digital PI controller,and Direct Digital Synthesis(DDS).The mathematical models of each component of the phase-locked loop are derived in detail in the paper to guide the implementation of Verilog modules and the selection of control parameters.Finally,the phase-locked performance of this loop in the frequency range from 1kHz to 1.1kHz is verified through simulation in Vivado 2023.2.。

关 键 词：全数字锁相环 FPGA FIR 数字PI控制器 数控振荡器 

分 类 号：TN752[电子电信—电路与系统]