面向低磨损存内计算的多状态逻辑门综合  

The Synthesis of Multiple Stateful Logic Gates for In-memory Computing with Low Wear

作　　者：赵安宁 许诺[1,2] 刘康 罗莉 潘炳征[1] 薄子怡 谭承浩 Zhao Anning;Xu Nuo;Liu Kang;Luo Li;Pan Bingzheng;Bo Ziyi;Tan Chenghao(School of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Key Laboratory of Advanced Microprocessor Chips and Systems(National University of Defense Technology),Changsha 410073)

机构地区：[1]国防科技大学计算机学院,长沙410073 [2]先进微处理器芯片与系统重点实验室(国防科技大学),长沙410073

出　　处：《计算机研究与发展》2025年第3期620-632,共13页Journal of Computer Research and Development

基　　金：国家自然科学基金项目(62202483);湖南省自然科学基金项目(2022JJ40563);武汉光电国家研究中心开放基金项目(2021WNLOKF019);PDL开放基金项目(WDZC20235250112)。

摘　　要：通过融合布尔逻辑和非易失存储的功能,忆阻状态逻辑电路可以消除计算过程中的数据移动,实现在存储器中计算,打破传统冯·诺依曼计算系统的“存储墙”和“能耗墙”.近年来,通过构建条件转变到数学逻辑关系之间的映射,已经有一系列存内状态逻辑门被提出,功能覆盖IMP,NAND,NOR,NIMP等多个逻辑运算.然而,复杂计算过程到存内状态逻辑实现的自动化综合映射方法仍处于萌芽阶段,特别是缺少针对器件磨损的探讨,限制了设备维修不便的边缘计算场景应用.为降低复杂存内状态逻辑计算过程的磨损(翻转率),实现了一种面向低磨损存内计算的多状态逻辑门综合映射过程.与领域内熟知的SIMPLER MAGIC状态逻辑综合流程相比,该综合映射流程在复杂计算过程的翻转率上实现了对EPFL,LGSynth91的典型基准测试电路分别平均35.55%,47.26%以上的改进;与最新提出的LOSSS状态逻辑综合流程相比,在复杂计算过程的翻转率上实现了对EPFL,LGSynth91的典型基准测试电路分别平均8.48%,6.72%以上的改进.By merging the functions of Boolean logic and non-volatile memory,memristive stateful logic can achieve the real sense of in-memory computing through eliminating data movement during computation,which breaks the“memory wall”and“energy wall”of traditional von Neumann computing system.In recent years,a series of the memristor-based in-memory stateful logic gates have been proposed by linking the conditional switching process and mathematical logic function,whose functions cover multiple logic functions such as IMP,NAND,NOR,and NIMP etc.However,the automated synthesis and mapping method for implementing the in-memory complex stateful logic computation by cascading the stateful logic gates is still embryonic,especially lacking the investigations on the device wear,which limits the application of in-memory stateful logic in edge computing scenarios.To reduce the device wear(toggle rate)in a complex in-memory stateful logic computation process,we propose a stateful logic synthesis and mapping process based on multiple stateful logic gates for low-wear in-memory computing.Compared with the two state-of-art stateful logic synthesis and mapping tools of SIMPLER MAGIC and LOSSS,the proposed low-wear logic synthesis and mapping process achieves an average improvement of over 35.55%and 8.48%in the toggle rates respectively under the EPFL combinational benchmark circuits.Moreover,the proposed tool achieves an average improvement of over 47.26%and 6.72%in the toggle rates respectively under the LGSynth91 benchmark circuits.

关 键 词：忆阻器 状态逻辑 翻转率 逻辑综合与映射 低磨损 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]