超薄存储芯片三维堆叠封装服役可靠性研究  

Research on service reliability of 3D stacked packaging for ultrathin memory chip

作　　者：曹峰哲 杨道国[1] CAO Fengzhe;YANG Daoguo(School of Mechanical and Electrical Engineering,Guilin University of Electronic Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学机电工程学院,广西桂林541004

出　　处：《桂林电子科技大学学报》2024年第5期519-524,共6页Journal of Guilin University of Electronic Technology

基　　金：广西创新驱动发展专项(桂科AA21077015)。

摘　　要：随着存储芯片频率和功率的日益增加,三维堆叠封装难以满足芯片的散热需求,易引起芯片翘曲、开裂甚至界面分层等失效问题,这会严重影响存储芯片的性能和使用寿命。针对上述问题,以典型的六层堆叠存储芯片封装结构为研究对象,研究了芯片在服役状态下的芯片结温和最大等效应力。其次,采用正交试验与灰色关联分析相结合的方法对封装结构的芯片结温与最大等效应力进行双目标优化设计,得到了其最优的封装结构参数组合。仿真结果表明,优化后的六层堆叠存储芯片封装结构的芯片结温下降了7.10%,最大等效应力下降了9.67%,对实际的堆叠封装工艺开发与产业化具有指导意义。With the increasing frequency and power of memory chips,3D stacked packaging is difficult to meet the heat dissipation requirements of the chip,which is easy to cause chip warpage,cracking,and even interface delamination and other failure problems,seriously affecting the performance and service life of memory chips.To solve the above problems,the typical six layer stacked memory chip packaging structure is taken as the research object,and the chip junction temperature and maximum equivalent stress of the chip in service state are studied.Secondly,the combination of orthogonal test and grey correlation analysis is used to optimize the junction temperature and maximum stress of the chip,and the optimal combination of parameters is obtained.The simulation results show that the junction temperature of the optimized six layer stacked memory chip package structure decreases by 7.10%,and the maximum equivalent stress decreases by 9.67%.And it has certain guiding significance to the actual process development and industrialization.

关 键 词：超薄存储芯片 三维堆叠封装 芯片结温 等效应力 可靠性 

分 类 号：TN304[电子电信—物理电子学]