高效HEVC编码器的硬件架构设计  

Hardware Architecture Design for HEVC Encoder

作　　者：黄晖 施隆照[1] 黄霖 HUANG Hui;SHI Long-zhao;HUANG Lin(College of Physics and Information Engineering,Fuzhou University)

机构地区：[1]福州大学物理与信息工程学院

出　　处：《中国集成电路》2025年第3期35-42,共8页China lntegrated Circuit

摘　　要：高效视频编码标准(High Efficiency Video Coding,HEVC)作为H.264/AVC的继任者,提高了约2倍的编码效率。但其编码数据的计算复杂度和依赖性的增加,使视频编码器在硬件实现上更加困难。尤其是对编码器视频数据的处理和存取以及编码器内部状态控制的实现带来挑战。本文基于HEVC的宏块编码流程,提出了一种满足整体编码器实时高效运行的视频数据的存取结构和协调编码器各模块的顶层控制的方案。整个设计基于VCS和VIVADO的联合仿真环境验证功能的正确性。并在Xilinx公司的VCU118型号的FPGA上完成上板验证。测试结果表明,综合后的编码器的主频为100 MHz,可以满足编码器实现1080P30@fps的编码需求。The High Efficiency Video Coding(HEVC)standard,the successor to H.264/AVC,improves coding efficiency by a factor of approximately two.However,the increased computational complexity and dependencies of its encoded data make video encoders more difficult to implement in hardware.In particular,the processing and access to the encoder video data and the implementation of the encoder's internal state control pose challenges.In this paper,we propose an access structure for the video data and coordinated top-level control of the encoder modules based on the macroblock encoding process of HEVC to meet the real-time and efficient operation of the overall encoder.The whole design is based on a joint simulation environment of VCS and VIVADO to verify the correctness of the functionality.It was also verified on board on a Xilinx model VCU118 FPGA.The test results show that the integrated encoder has a main frequency of 100 MHz and can meet the encoding requirements of 1080P30@fps.

关 键 词：视频编码 HEVC DDR FPGA 

分 类 号：TN919.81[电子电信—通信与信息系统]