低抖动锁相环建模设计  

Modeling and Design of Low Jitter PLL

作　　者：李龙宇 郭浩东 张霞[1] LI Longyu;GUO Haodong;ZHANG Xia(School of Physics Science and Information Engineering,Liaocheng University,Liaocheng 252000,China)

机构地区：[1]聊城大学物理科学与信息工程学院,山东聊城252000

出　　处：《河南科技》2025年第3期5-9,共5页Henan Science and Technology

摘　　要：【目的】深入研究锁相环(PLL)理论与设计,重点探讨其在现代集成电路系统中发挥的作用,设计出一种低抖动电荷泵锁相环(CPPLL)。【方法】在鉴频鉴相器设计过程中,从鉴频鉴相器、电荷泵、压控振荡器(VCO)、低通滤波器(LPF)、分频器等方面出发,进行详细分析和建模。通过增加复位信号通路上的延迟来减小鉴相死区,从而降低压控振荡器的电压纹波。采用二阶RC滤波器作为环路滤波器优化噪声,并采用计数器作为分频器,对锁相环进行系统级建模及仿真分析。在仿真完成后,对锁相环各模块进行噪声分析。【结果】在输入信号为10 MHz的前提下,锁相环锁定时间为7μs,输出频率为250 MHz。【结论】该研究不仅为高速数据传输技术中的锁相环设计提供有效的设计方案,也为其他领域锁相环的应用提供参考和借鉴。[Purposes]This paper deeply studies the theory and design of phase locked loop(PLL),and focuses on its key role in modern integrated circuit systems to design a low jitter charge pump phase-locked loop(CPPLL).[Methods]In the design process of phase frequency detector,the detailed analysis and modeling are carried out from the aspects of the phase frequency detector,charge pump,voltage-controlled oscillator(VCO),low-pass filter(LPF)and divider.And the dead time of phase discrimination is reduced by increasing the delay on the reset signal path,to reduce the voltage ripple of VOC.The second-order RC filter is used as the loop filter to optimize the noise.In the frequency divider part,the counter is used as the frequency divider.Finally,the PLL is modeled and simulated at the system level.After the completion of system level simulation,the noise of each module of PLL is analyzed.[Findings]On the premise that the input signal is 10 MHz,the locking time of PLL is 7μs and the output frequency is 250 MHz.[Conclusions]The research in this paper not only provides an effective design scheme for PLL in high-speed data transmission technology,but also provides a reference for the application of PLL in other fields.

关 键 词：低抖动 锁相环 建模 

分 类 号：TN492[电子电信—微电子学与固体电子学]