基于FPGA与PCIe的回波模拟器采集组件设计  

Design of acquisition component for echo simulator based on FPGA and PCIe

作　　者：李森 王建明 唐吉林 LI Sen;WANG Jianming;TANG Jilin(Automation Research Institute Co.,Ltd.,China South Industries Group Corporation,Mianyang 621000,China)

机构地区：[1]中国兵器装备集团自动化研究所有限公司,四川绵阳621000

出　　处：《空天预警研究学报》2025年第1期67-73,共7页JOURNAL OF AIR & SPACE EARLY WARNING RESEARCH

摘　　要：针对雷达回波模拟器采集组件控制器局域网(CAN)通信接口总线利用率不高的问题,提出一种“流水型指令、数据配置+自动读取”的回波模拟器采集组件设计方法.采用8片模数转换器(ADC)芯片,对8个通道的数据进行并行实时采样;采用快速中值平均滤波算法,达到ADC数据滤波低延时的要求;针对回波模拟器采集组件用户数据报(UDP)协议通信功能,设计支持10/100/1000 Mbps三速自适应的以太网UDP协议栈.最后将该方法在现场可编程门阵列(FPGA)上进行设计与实现.实际测试结果表明:CAN通信接口的总线利用率由原有的42.29%提升到79.80%;ADC数据的滤波延迟仅为一个时钟周期,且相位对齐;UDP协议栈通信功能正确满足设计要求.Aimed at the problem of low bus utilization of the Controller Area Network(CAN)communication interface of the radar echo simulator acquisition component,a design method of“pipelining instruction,data configuration+automatic reading”for the echo simulator acquisition component is proposed.Eight analog-to-digital converter(ADC)chips are used to perform parallel real-time sampling of data from eight channels.A fast median average filtering algorithm is adopted to meet the low-delay requirement of ADC data filtering.For the User Datagram Protocol(UDP)communication function of the echo simulator acquisition component,an Ethernet UDP protocol stack supporting 10/100/1000 Mbps three-speed adaptive is designed.Finally,this method is designed and implemented on the Field Programmable Gate Array(FPGA).The actual test results show that the bus utilization of the CAN communication interface is increased from the original 42.29%to 79.80%,that the filtering delay of ADC data is only one clock cycle,and the phase is aligned,and that the communication function of the UDP protocol stack correctly meets the design requirements.

关 键 词：现场可编程门阵列 外设组件互连扩展总线 控制器局域网通信 快速中值滤波 UDP协议栈 

分 类 号：TN955[电子电信—信号与信息处理]