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作 者:卞玲艳 蔡莹 周倩蓉 陆霄 BIAN Lingyan;CAI Ying;ZHOU Qianrong;LU Xiao(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214072,China)
机构地区:[1]中国电子科技集团公司第五十八研究所,江苏无锡214072
出 处:《电子设计工程》2025年第6期25-29,共5页Electronic Design Engineering
摘 要:针对系统级封装尺寸小、供电电压低、工作电流大以及对电源完整性要求高的特殊性,对SIP(System in Package)中基板设计进行电源仿真和优化。通过仿真指导基板设计,提高SIP产品的设计成功率,缩短设计周期。通过Power DC软件进行了直流压降和电流密度的仿真分析,根据电源完整性相关理论,讨论基板设计中电源平面的影响因素,结合版图分析,给出实际的优化方案,并经过仿真迭代验证,使所设计的基板满足产品性能要求。In view of the particularity of small system-level package size,low power supply voltage,high working current and high requirements for power integrity,power simulation and optimization were carried out for substrate design in System in Package(SIP).Through simulation to guide the design of the substrate,improve the success rate of SIP product design and reduce the design cycle.Power simulation analysis was carried out through Cadence Power DC software.The influence factors of supply in substrate design was discussed based on the theory of power integrity.The actual optimization scheme was given by combining with layout analysis.The designed substrate could meet the power requirements of a SIP product performance.
关 键 词:SIP系统级封装 电源仿真 电源完整性 电源分布网络
分 类 号:TN43[电子电信—微电子学与固体电子学]
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