A 0.0012-mm^(2) 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of f_(carrier)/2  

作　　者：Xinyu Shen Zhao Zhang Jie Yang Jian Liu Nanjian Wu Mohamad Sawan Liyuan Liu 

机构地区：[1]State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100049,China [2]Center of Materials Science and Optoelectronics Engineering,University of Chinese Academy of Sciences,Beijing 100049,China [3]CenBRAIN Neurotech,School of Engineering,Westlake University,Hangzhou 310024,China

出　　处：《Journal of Semiconductors》2025年第3期61-67,共7页半导体学报(英文版)

基　　金：supported by the National Natural Science Foundation of China under grant 62222409 and 62174153;by Key Research Program of Frontier Sciences, CAS, under grant ZDBS-LY-JSC008。

摘　　要：This paper presents a compact ultra-low-power phase-locked loop (PLL) based binary phase-shift keying(BPSK)demodulator. The loop-filter-less(LPF-less) PLL is proposed to make phase of PLL output carrier signal track the phase of BPSK signal in real time. Thus, the maximum date rate can be significantly extended to the half of the carrier frequency(f_(carrier)) with a very compact size compared to prior PLL-based BPSK demodulators. Furthermore, eliminating all the static power in our LPF-less PLL, the energy efficiency is obviously improved. Fabricated in a 40-nm CMOS process, our prototype occupies 0.0012-mm^(2)core active area, and achieves the maximum data rate of 6.78 Mb/s (f_(carrier)/2) at f_(carrier)of 13.56 MHz. The power consumption and energy efficiency is 4.47 μW and 0.66 pJ/bit at 6.78-Mb/s data rate, respectively.

关 键 词：BPSK PLL loop filter compact LOW-POWER DEMODULATOR wireless power transmission(WPT) 

分 类 号：TN40[电子电信—微电子学与固体电子学] TN713