FPGA芯片SRIO总线接口的仿真测试平台研究  

Research on the Simulation Testing Platform for SRIO Bus Interface of FPGA Chip

作　　者：李洋[1] 王琪[1] 阳徽 LI Yang;WANG Qi;YANG Hui(Beijing Institute of Aerospace Automatic Control,Beijing 100854,china)

机构地区：[1]北京航天自动控制研究所,北京100854

出　　处：《电子质量》2025年第2期12-18,共7页Electronics Quality

摘　　要：现场可编程逻辑门阵列(FPGA)的大数据量传输常采用串行高速输入/输出(SRIO)总线,目前FPGA芯片的SRIO总线接口仿真测试存在环境搭建复杂、测试覆盖性低、数据判读复杂、人员学习协议成本高等问题,极大降低了FPGA的验证效率。研究了FPGA仿真测试平台方案,采用SystemVerilog、perl脚本和SVA语言相结合的方式,构建了FPGA软件SRIO总线自动化仿真验证平台框架,嵌入全套测试脚本,可实现FPGA仿真测试平台的自动搭建,SRIO总线不同配置、不同事务类型的全面性验证,模拟测试特征数据帧生成,总线协议结果自动判别。该平台可有效缩短FPGA软件的测试时间和调试周期,提高验证质量。Serial rapid input/output(SRIO)bus is often used for large data transmission in field programmable gate array(FPGA)software.At present,the simulation testing of SRIO bus interface of FPGA chips has problems,such as complex environment construction,low testing coverage,complex data interpretation,and high cost of personnel learning protocols,etc,which greatly reduces the efficiency of FPGA verification.The FPGA simulation testing platform scheme is studied,and SystemVerilog,Perl script and SVA language are used to build an FPGA software SRIO bus automation simulation platform framework.A complete set of test scripts are embedded,which can achieve automatic construction of FPGA simulation testing platform,comprehensive verification of SRIO bus with different configurations and transaction types,generation of simulation test feature data frames,and automatic discrimination of bus protocol results.This platform can effectively shorten FPGA software testing time and debugging cycle,and improve verification quality.

关 键 词：现场可编程逻辑门阵列 串行高速输入/输出总线 仿真测试平台 自动化搭建 全面性验证 协议自动判别 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]