5G定位算法的FPGA加速设计研究  

The linear leastsquares positioning algorithm based on FPGA

作　　者：冯洲武 崔默涵 陈涛[1] 朱逸飞 赵昆[1] FENG Zhouwu;CUI Mohan;CHEN Tao;ZHU Yifei;ZHAO Kun(School of Electronics and Communication Engineering,East China Normal University,Shanghai 200241,China)

机构地区：[1]华东师范大学通信与电子工程学院,上海200241

出　　处：《微电子学与计算机》2025年第3期68-74,共7页Microelectronics & Computer

基　　金：上海市浦东新区科技和经济委员会项目(PKX2019-R10);浦东新区科技发展基金产学研专项(PKX2023-D07)。

摘　　要：在大数据和5G时代背景下,对于线性最小二乘定位算法(Linear Least Squares,LLS)在FPGA(Field-Programmable Gate Array,现场可编程门阵列)上的加速研究,是一项具有挑战性且意义重大的工作。FPGA由于其可编程性、高性能和高能效比的特点,为解决5G实时计算提供了一个可行的方案。基于以上背景,为了解决面向异构平台的线性最小二乘定位算法加速问题,开展了基于线性最小二乘定位算法的FPGA设计研究,以在现实基站中更好的部署线性最小二乘定位算法。为了减少算法部署的硬件资源,首先对基站采集数据进行了优化预处理,然后提出了基于固定基元的FPGA硬件程序优化方法。在虹口区真实数据集上开展了抽取实验。实验结果表明:利用基于固定基元的FPGA硬件程序优化方法,其预处理时间、方程解算时间相较于传统的CPU计算减少了99.5%,计算误差在1 m以内,资源相对于原本的硬件部署方法减少50%。In the context of big data and 5G era,it is a challenging and significant task to study the accelerated implementation of Linear Least Squares(LLS)algorithms on FPGA(Field-Programmable Gate Array).Due to its programmability,high performance,and high energy efficiency,FPGA provides a feasible solution to solve the real-time and complexity problems in 5G computing.Based on the above background,in order to solve the acceleration problem of linear least squares positioning algorithm for heterogeneous platforms,the FPGA design based on linear least squares positioning algorithm is carried out to better deploy the linear least squares localization algorithm in real base stations.In order to reduce the hardware resources of the algorithm deployment,the data collected by the base station is optimized and preprocessed first,and then the FPGA hardware program optimization method based on fixed primitive is proposed.The extraction experiment is carried out on the real dataset in Hongkou district.Using a fixed element based FPGA hardware program optimization method,the preprocessing time and equation solving time are reduced by 99.5%compared to traditional CPU calculations,with a calculation error of less than 1m,and resources are reduced by 50%compared to the original hardware deployment method.

关 键 词：FPGA 线性最小二乘 固定基元 

分 类 号：TN91[电子电信—通信与信息系统]