多调制方式兼容的BCH概率软译码器的FPGA实现  

FPGA implementation of a BCH probabilistic soft decoder compatible with multiple modulation modes

作　　者：庞宇[1] 张洋[1] 李国权[1] 杨家斌 PANG Yu;ZHANG Yang;LI Guoquan;YANG Jiabin(Photoelectronic Information Sensing and Transmission Technology Laboratory,Chongqing University of Posts and Telecommunications,Chongqing 400065,China)

机构地区：[1]重庆邮电大学光电信息感测与信息传输实验室,重庆400065

出　　处：《微电子学与计算机》2025年第3期75-83,共9页Microelectronics & Computer

基　　金：国家自然科学基金(61671091)。

摘　　要：为实现在复杂环境下多种人体体征参数的高可靠性传输,设计了一种基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的BCH概率软译码器。译码器利用概率计算的方式替换Chase算法中的大量排序运算,并利用8位循环冗余校验(Cyclic redundancy check,CRC-8)实现迭代译码。译码器包括信道信息输入模块、软解映射模块、概率比特序列生成模块、BCH硬译码模块、以及CRC-8提前终止判决模块,可同时满足二进制相移键控(Binary Phase Shift Keying,BPSK)、π/4-四相相对相移键控(π/4-Differential Quadrature Phase Shift Keying,π/4-DQPSK)两种调制方式的BCH译码。MATLAB仿真表明,在误块率为10^(−2)情况下,译码器与现有的Chase算法和硬译码算法相比分别有约0.9 dB、1.4 dB的性能增益。完成了基于FPGA的硬件设计。译码器使用全并行处理,逻辑结构简单,在相同译码速度条件下硬件消耗资源较Chase算法降低约20%。In order to realize highly reliable transmission of multiple human physical parameters in complex environments,a BCH probabilistic soft decoder based on Field Programmable Logic Gate Array(FPGA)is designed.The decoder uses probabilistic calculation to replace a large number of sorting operations in the Chase algorithm,and realizes iterative decoding using 8-bit cyclic redundancy check(CRC-8).The decoder includes a channel information input module,a soft demapping module,a probabilistic bit sequence generation module,a BCH hard decoding module,and a CRC-8 early termination judgment module,which can simultaneously satisfy the requirements of Binary Phase Shift Keying(BPSK),π/4-Differential Quadrature Phase Shift Keying(π/4-DQPSK).MATLAB simulations show that the decoder has a performance gain of about 0.9 dB and 1.4 dB compared with the existing Chase algorithm and hard decoding algorithm,respectively,at an error block rate of 10^(−2).The FPGA-based hardware design is completed.The decoder uses fully parallel processing with a simple logic structure,which reduces the hardware consumption resources by about 20%compared with the Chase algorithm under the same decoding speed condition.

关 键 词：BCH码 软译码 概率计算 FPGA 

分 类 号：TN911.2[电子电信—通信与信息系统]