基于可跨层重构LFSR的3D-SIC内建自测试方案  

3D-SIC built-in self-test scheme based on cross-layer reconfigurable LFSR

作　　者：陈田[1,2] 罗蓓蓓 刘军[1,2] 鲁迎春[3] CHEN Tian;LUO Beibei;LIU Jun;LU Yingchun(School of Computer and Information,Hefei University of Technology,Hefei 230009,China;Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine,Hefei University of Technology,Hefei 230009,China;School of Microelectronics,Hefei University of Technology,Hefei 230009,China)

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009 [2]合肥工业大学情感计算与先进智能机器安徽省重点实验室,安徽合肥230009 [3]合肥工业大学微电子学院,安徽合肥230009

出　　处：《微电子学与计算机》2025年第3期100-109,共10页Microelectronics & Computer

基　　金：国家自然科学基金(62174048,62027815)。

摘　　要：针对三维堆叠集成电路(Three-Dimensional Stacked Integrated Circuits,3D-SIC)中测试面积开销和测试数据存储量大的问题,对于n层3D-SIC,提出了一种基于可跨层重构线性反馈移位寄存器(Cross-Layer Reconfigurable Linear Feedback Shift Register,CLR-LFSR)的内建自测试(Built-In Self-Test,BIST)结构。在键合中和键合后测试阶段,可以任意组合键合前测试阶段中的LFSR,连接构成级数更大的LFSR结构,以提高包含确定位更多的测试向量的编码成功率。同时,还提出了一种设置阈值的相容压缩和最优分级重播种结合的测试数据压缩方法。通过在测试向量图着色相容时设置相容阈值,然后将相容后的测试向量按照包含的确定位个数分成2^(n)−1组,重播种生成长度不定的种子集,从而减少了测试数据存储量。在ISCAS'89电路上的实验结果表明,相对于不可重构的BIST方法,方案能够减少三维芯片43.8%的面积开销,测试数据存储量减少98.52%。To address the issues of large test area overhead and significant test data storage requirements in Three-Dimensional Stacked Integrated Circuits(3D-SIC),for n-layer 3D-SIC,a Built-In Self-Test(BIST)structure based on the Cross-Layer Reconfigurable Linear Feedback Shift Register(CLR-LFSR)is proposed.During the mid-bond and post-bond test phases,LFSRs from the pre-bond test phase can be arbitrarily combined and connected to form an LFSR structure with a larger number of stages to improve the coding success rate of test patterns containing more deterministic bits.Meanwhile,a test data compression method is proposed,which combines compatibility compression with a set threshold and optimal hierarchical reseeding.By setting the compatibility threshold,the post-compatibility test patterns are divided into 2^(n)−1 groups based on the number of deterministic bits and then reseeded to generate a seed set of variable lengths,which reduces the test data storage capacity.The experimental results on the ISCAS'89 benchmark circuits demonstrate that,in comparison to the traditional non-reconfigurable BIST approach,the proposed method achieves a 43.8%reduction in the area overhead of 3D chips and a 98.52%decrease in test data storage requirements.

关 键 词：可跨层重构LFSR BIST 测试数据压缩 3D-SIC测试 

分 类 号：TN47[电子电信—微电子学与固体电子学]