基于UCIe的一种低延时Chiplet接口设计  

Design of a low delay Chiplet interface based on UCIe

作　　者：秦和洋 唐磊[1] 匡乃亮 梁勇 QIN Heyang;TANG Lei;KUANG Nailiang;LIANG Yong(Xi'an Microelectronics Technology Institute,Xi'an 710054,China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2025年第3期110-116,共7页Microelectronics & Computer

摘　　要：近年来,芯粒作为通过工艺改进来解决摩尔定律失效的一种方法被越来越多的人关注。通用芯粒互连协议(Universal Chiplet Interconnect Express,UCIe)的提出为芯粒之间的互连接口标准提供了解决方案。由于在UCIe有大量的协议判断的信号,会造成一些额外的延时,会影响在各个芯粒之间的传输效率。为此,通过优化UCIe协议,将协议层设置为默认的PCIe协议,使得两个支持PCIe接口的芯粒直接进行数据传输。采用硬件描述语言Verilog HDL设计并实现了该结构。仿真结果表明,在整个结构正常运行过程中,改进后的结构展现出了更加优异的性能,协议层可以降低大约90%的延时。In recent years,chiplet has been paid more and more attention as a method to solve the failure of Moore's Law through process improvement.The proposal of Universal Chiplet Interconnect Express(UCIe)provides a solution for the interconnection interface standard between chiplets.Due to the large number of protocol judgment signals in UCIe,some additional delay will be caused,which will affect the transmission efficiency between the individual chiplets.Therefore,the UCIe protocol is optimized and the protocol layer is set as the default PCIe protocol,so that the two chiplets supporting PCIe interfaces can directly transmit data.The structure is designed and implemented by Verilog HDL,a hardware description language.The simulation results show that the improved structure exhibits better performance during the normal operation of the whole structure,and the protocol layer can reduce about 90%delay.

关 键 词：芯粒 UCIe PCIE 原型验证 

分 类 号：TN492[电子电信—微电子学与固体电子学]