稳定STO振荡的前端读出ASIC芯片设计  

Design of Front-end Readout ASIC for Stabilizing STO Oscillations

作　　者：夏倩倩 曾蕙明 XIA Qianqian;ZENG Huiming(School of Electronics&Information Engineering,Nanjing University of Information Science&Technology,Nanjing 210044,China;School of Integrated Circuit Science and Engineering,Wuxi University,Wuxi 214015,China)

机构地区：[1]南京信息工程大学电子与信息工程学院,江苏南京210044 [2]无锡学院集成电路科学与工程学院,江苏无锡214015

出　　处：《无线电工程》2025年第3期511-519,共9页Radio Engineering

基　　金：国家重点研发计划青年科学家项目(2023YFB2407700)。

摘　　要：自旋转矩振荡器(Spin-Torque Oscillator,STO)具有超小尺寸、低功耗和宽调谐范围等优点,因而有望成为新一代微波信号源。但是在自由运行振荡下,STO的相位噪声较大,无法满足实际的微波应用。针对这一问题,设计了一颗应用于稳定STO振荡的前端读出ASIC芯片,该数模混合芯片主要由可变增益放大器(Variable Gain Amplifier,VGA)和全数字锁相环(All-Digital Phase-Locked Loop,ADPLL)组成,选用ADPLL的原因是数字电路与模拟电路相比,具有灵活的可扩展性、更好的跨工艺设计、可移植性以及面积更小等优点。仿真结果表明,相较于传统的模拟锁相环(Phase-Locked Loop,PLL),ADPLL将整体电路功耗降低为0.704μW;将PLL中心频率设置为300 MHz时,带宽为2.5 MHz,与类似系统相比提高了5倍以上。Spin-Torque Oscillator(STO)has the advantages of ultra-small size,low power consumption and wide tuning range,and thus is expected to be a new generation of microwave signal source.However,under free-running oscillations,the phase noise of STO is large,which cannot satisfy the requirement for practical microwave applications.To address this problem,a front-end readout ASIC chip is designed for stabilizing STO oscillations.The digital-analog hybrid chip is mainly composed of a Variable Gain Amplifier(VGA)and an All-Digital Phase-Locked Loop(ADPLL),and the ADPLL is selected for its flexibility,scalability,better cross-process design,portability,and smaller area compared with analog circuits.Simulation results show that by using the ADPLL,the overall circuit power consumption is reduced to 0.704μW compared with the traditional analog Phase-Locked Loop(PLL);the bandwidth is 2.5 MHz when the center frequency of the PLL is set to 300 MHz,which is more than five times higher compared with similar systems.

关 键 词：自旋转矩纳米振荡器 适应锁相环系统 ASIC芯片 

分 类 号：TN99[电子电信—信号与信息处理]