一种基于帧结构的并行FIR数字滤波的FPGA实现  

FPGA Implementation of Parallel FIR Digital Filtering Based on Frame Structure

作　　者：胡春江 刘宪军 张丁丁 李炎桦 黎伟 HU Chunjiang;LIU Xianjun;ZHANG Dingding;LI Yanhua;LI Wei(Southwest China Research Institute of Electronic Equipment,Chengdu,Sichuan 610036,China)

机构地区：[1]西南电子设备研究所,四川成都610036

出　　处：《自动化应用》2025年第6期236-239,共4页Automation Application

摘　　要：针对FPGA内直接型FIR滤波架构数据吞吐速率慢、数据带宽受限,传统并行FIR滤波架构实现逻辑复杂、硬件资源消耗大的问题,提出了一种基于帧结构的并行FIR数字滤波架构。通过从流水输入的数据中提取滑动帧进行滑动滤波,并根据帧结构对滑动滤波输出进行拼接、截取,所提滤波架构可以获得与传统并行FIR滤波架构几乎相同的频域响应。而相较于传统并行架构,所提架构消耗的系统资源更少,工程上更易实现。基于MATLAB和ISE的仿真实验结果证明了所提滤波架构的有效性。Aiming at the problems of slow data throughput rate and limited data bandwidth of direct-type FIR filtering architecture within FPGA,and complex implementation logic and high hardware resource consumption of traditional parallel FIR filtering architecture,a parallel FIR digital filtering architecture based on frame structure is proposed.By extracting sliding frames from the flowing input data for sliding filtering,and splicing and intercepting the sliding filter output according to the frame structure,the proposed filtering architecture can obtain almost the same frequency domain response as that of the traditional parallel FIR filtering architecture.Compared with the traditional parallel architecture,the proposed architecture consumes less system resources and is easier to implement in engineering.Simulation experiments based on MATLAB and ISE demonstrate the effectiveness of the proposed filtering architecture.

关 键 词：FIR数字滤波 FPGA 并行架构 

分 类 号：TN911.7[电子电信—通信与信息系统]