基于ASD芯片的前端电路设计与测试  

Front-end Circuit Design and Test Based on ASD Chip

作　　者：蒋洪灿 马冬梅[1] 孔洁[2] 许佳鹏 王世陶[2] 马朋[2] 刘相满 颜俊伟 JIANG Hongcan;MA Dongmei;KONG Jie;XU Jiapeng;WANG Shitao;MA Peng;LIU Xiangman;YAN Junwei(College of Physics and Electronic Engineering,Northwest Normal University,Lanzhou 730070,China;Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China)

机构地区：[1]西北师范大学物理与电子工程学院,兰州730070 [2]中国科学院近代物理研究所,兰州730000

出　　处：《原子核物理评论》2024年第4期1033-1039,共7页Nuclear Physics Review

基　　金：国家自然科学基金资助项目(U2031206)。

摘　　要：为提高HIRFL-CSR外靶实验终端径迹探测器多丝漂移室MWDC前端读出电子学的集成度和动态范围,设计基于ASD芯片的32通道板载前端电路,用于验证ASD+HPTDC的读出方案替代现有SFE16+HPTDC的可行性。该电路主要包括保护电路、时间转换电路、差分驱动电路。目前已在实验室条件下完成电子学性能测试,包括动态范围内的时间精度测试,两种阈值下的时间精度测试及前沿抖动性能测试。结果表明,32通道前端电路实现处理的动态范围可达1200 fC,前沿抖动的时间分辨率优于80 ps;在动态范围100~1200 fC和阈值0.3 V条件下,TOT抖动的Sigma优于150 ps。To improve the integration and dynamic range of the front-end readout electronics of the Multi-Wire Drift Chamber(MWDC)in the track detector for the external target experiment at HIRFL-CSR,a 32-channel on-board front-end circuit based on the ASD chip was designed to verify the feasibility of the ASD(Amplifier Shaper Discriminator)+HPTDC(High-Performance TDC)readout scheme as a replacement for SFE16+HPTDC.The circuit primarily consists of a protection circuit,time conversion circuit,and differential driver circuit.Electronic performance tests have been completed under laboratory conditions,including the time accuracy test across the dynamic range,the time accuracy test at two threshold values,and the leading-edge jitter performance test.Test results demonstrate that the 32-channel front-end circuit achieves a dynamic range of 1200 fC,with a leading-edge jitter time resolution better than 80 ps.Moreover,under a threshold of 0.3 V and a dynamic range of 100 to 1200 fC,the sigma of TOT jitter is better than 150 ps.

关 键 词：时间过阈 ASD 动态范围 时间分辨率 前沿抖动 

分 类 号：TL824[核科学技术—核技术及应用]