RVAM16:a low-cost multiple-ISA processor based on RISC-V and ARM Thumb  

作　　者：Libo HUANG Jing ZHANG Ling YANG Sheng MA Yongwen WANG Yuanhu CHENG 

机构地区：[1]College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China

出　　处：《Frontiers of Computer Science》2025年第1期41-51,共11页计算机科学前沿(英文版)

基　　金：supported in part by the National Natural Science Foundation of China(Grant Nos.62272475,62090023,and 62172430);the National Key R&D Program of China(No.2021YFB0300300);the Natural Science Foundation of Hunan Province of China(Nos.2022JJ10064 and 2021JJ10052);the STIP of Hunan Province(No.2022RC3065);the Key Laboratory of Advanced Microprocessor Chips and Systems.

摘　　要：The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field.To address this challenge,one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs.However,due to constraints in cost and performance,the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems.By exploring the RISC-V and ARM Thumb ISAs,this paper proposes RVAM16,which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique.The results show that,when running non-native ARM Thumb programs,RVAM16 achieves a significant speedup of over 2.73×with less area and energy consumption compared to using hardware binary translation alone,reaching more than 70%of the performance of native RISC-V programs.

关 键 词：multiple-ISA processor architecture binary translation RISC-V embedded 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]