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作 者:姜冬瑞 张锐浩 武靖 赵富成 张会新[1] JIANG Dongrui;ZHANG Ruihao;WU Jing;ZHAO Fucheng;ZHANG Huixin(Key Laboratory of Instrumentation Science&Dynamic Measurement,Ministry of Education,North University of China,Taiyuan 030051)
机构地区:[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051
出 处:《舰船电子工程》2025年第2期113-118,177,共7页Ship Electronic Engineering
基 金:国家自然科学基金青年科学基金项目(编号:51705475)资助。
摘 要:由于CMOS工艺的限制,图像传感器输出的原始数据往往带有噪声,需要进行滤波处理。双边滤波算法在图像降噪的同时也可以一定程度上保持边缘细节。效果优于均值滤波、高斯滤波等降噪算法。但是由于双边滤波的权重不仅考虑了窗口内像素的位置对中心像素的影响,还考虑了像素范围域中的辐射差异,导致算法的计算复杂度相对较高,对视频显示处理等高实时应用带来严峻挑战。针对此问题,该设计以Xilnx公司的Zynq系列ARM+FPGA异构SoC作为实现平台,充分发挥异构SoC的架构优势进行算法的加速设计,使用Vivado HLS进行接口为AXI4-Stream的双边滤波处理算法IP核的开发。在Zynq7020平台,时钟频率50 M,处理400^(*)400@30 fps的OV6946内窥镜摄像头输出的视频流,延时约为3.7 ms,实时性较高,并且在保留细节的同时较好地实现了去噪效果。Due to the limitations of the CMOS process,the raw data output by the image sensor often contains noise and needs to be filtered.The bilateral filtering algorithm can also maintain edge details to a certain extent while reducing image noise.The effect is better than noise reduction algorithms such as mean filter and Gaussian filter.However,since the weight of bilateral filtering not only considers the impact of the position of the pixel in the window on the central pixel,but also takes into account the radiation difference in the pixel range domain,the computational complexity of the algorithm is relatively high,which brings serious challenges to high real-time applications such as video display processing.In response to this problem,this design uses Xilnx's Zynq series ARM + FPGA heterogeneous SoC as the implementation platform,giving full play to the architectural advantages of the heterogeneous SoC to accelerate the design of the algorithm,and uses Vivado HLS to develop IP cores for the bilateral filtering processing algorithm with the interface of AXI4-Stream.On the Zynq7020 platform,the clock frequency is 50 M,and the video stream output by the OV6946 endoscope camera is processed at 400~*400@30 fps.The delay is about 3.7 ms,and the real-time performance is high.And it achieves a better denoising effect while retaining details.
关 键 词:FPGA 图像降噪 Zynq Vivado HLS 视频图像处理
分 类 号:TN919.5[电子电信—通信与信息系统]
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