埋入式晶圆级封装芯片翘曲有限元仿真及参数敏感性分析  

Finite Element Simulation and Parametric Sensitivity Analysis of Chip Warpage in Embedded Wafer Level Packaging

作　　者：吴道伟 李贺超 李逵 张雨婷 代岩伟 秦飞[2] Wu Daowei;Li Hechao;Li Kui;Zhang Yuting;Dai Yanwei;Qin Fei(Xi'an Microelectronics Technology Institute,Xi'an 710054,China;Institute of Electronic Packaging Technology and Reliability,Bejing University of Technology,Beijing 100124,China)

机构地区：[1]西安微电子技术研究所,西安710054 [2]北京工业大学电子封装技术与可靠性研究所,北京100124

出　　处：《半导体技术》2025年第4期399-406,共8页Semiconductor Technology

基　　金：北京市自然科学基金-小米创新联合基金(L243030)。

摘　　要：作为系统级封装(SiP)的关键技术之一,芯片埋置技术在提高I/O接口数量方面发挥着重要作用。伴随加工工艺温度变化,埋置芯片产生一定程度的翘曲,导致后续铺层的破损,使产品良率降低。针对埋入式晶圆级封装芯片在加工过程中的翘曲行为进行了模拟和研究。采用均匀化等效建模进行了有限元模拟,并结合输入参数变化和正交实验分析,研究了材料的弹性模量对芯片翘曲的影响。研究结果表明,芯片粘结薄膜(DAF)和钝化层(PL)的弹性模量对埋置芯片的翘曲起主要作用,为降低埋入式晶圆级封装芯片翘曲提供了参考。As one of the typical packaging technologies in system-in-package(SiP),chip-embedded technology plays an important role in increasing the number of I/O intevfaces.The warpage of embedded chip may become a certain degree of warpage during the change of processing temperature,leading to the damage of the subsequent layer,thus to reduce the yield of the product.The warpage behavior of wafer-level package chip during manufacturing processing was simulated and studied.Finite element simulation was performed through homogenized equivalent modeling,and the effect of elastic modulus of materials on chip warpage was investigated by combining input parameter changes and orthogonal experimental analysis.It isdemonstrate that the elastic modulus of the die attach film(DAF)and the passive layer(PL)play a major role in the warpage of embedded chip,which provides reference for the reduction of the warpage for the embedded wafer level packaging chip.

关 键 词：芯片埋置 翘曲 均匀化等效 正交实验 有限元分析 

分 类 号：TN405[电子电信—微电子学与固体电子学]