一款适用于高速读出电路的锁相环设计  

A phase-locked loop design for high-speed readout circuits

作　　者：方凯[1,2] 董瑞清 李敬国[2] FANG Kai;DONG Rui-qing;LI Jing-guo(Shandong University,Jinan 250000,China;North China Research Institute of Electro-Optics,Beijing 100015,China)

机构地区：[1]山东大学,济南250000 [2]华北光电技术研究所,北京100015

出　　处：《激光与红外》2025年第3期388-394,共7页Laser & Infrared

摘　　要：随着红外探测器系统读出电路的数字化发展,读出电路为保证数字信号的运算、传输和存储等处理的正确进行,对时钟信号的要求越来越高。本文基于综合性能良好的电荷泵锁相环结构设计了一款高速时钟信号产生电路,实现在晶振输入20 MHz参考时钟信号的条件下,锁相环快速锁定并稳定输出一个640 MHz低噪声高速时钟信号。本设计基于SMIC0.18μm工艺,仿真结果表明:在电源电压1.8 V下,总功耗小于5 mW,锁相环锁定后的控制电压纹波保持在500μV以内,锁定时间为4μs,相位噪声小于-99 dBc/Hz@1MHz,时钟抖动小于5 ps。With the digital development of readout circuits in infrared detector systems,the requirements for clock signals in readout circuits are becoming increasingly stringent to ensure accurate processing of digital signals,including computation,transmission,and storage.In this paper,a high-speed clock signal generation circuit based on a charge pump phase-locked loop structure with excellent comprehensive performance is designed to achieve fast locking and stable output of a 640 MHz low-noise high-speed clock signal under the condition of a 20 MHz reference clock signal from the crystal oscillator.The designed is based on SMIC 0.18μm process,and the simulation result shows that total power consumption is less than 5 mW at 1.8 V power supply,the control voltage ripple after the phase-locked loop is kept within 500μV,the locking time is 4μs,the phase noise is less than-99 dBc/Hz@1MHz,and the clock jitter is less than 5 ps.

关 键 词：ROIC 电荷泵锁相环 高速时钟信号 

分 类 号：TN215[电子电信—物理电子学] O436[机械工程—光学工程]