Low-noise and high-rate front-end ASIC for APD detectors in STCF ECAL  

作　　者：Chao Liu Ran Zheng Jia Wang Xiao-Min Wei Fei-Fei Xue Rui-Guang Zhao Yann Hu 

机构地区：[1]School of Computer Science and Technology,Northwestern Polytechnical University,Xi’an 710072,China [2]Research and Development Institute of Northwestern Polytechnical University in Shenzhen,Shenzhen 518063,China [3]School of Electronics and Information,Northwestern Polytechnical University,Xi’an 710072,China

出　　处：《Nuclear Science and Techniques》2025年第4期127-139,共13页核技术(英文)

基　　金：supported by the National Natural Science Foundation of China(Nos.12375191,12275218,12341502,12105224,12205307);National Key Research and Development Program of China(No.2023YFE0206300,2023YFF0719600);Guangdong Basic and Applied Basic Research Foundation(No.2024A1515012141);China Postdoctoral Science Foundation(No.2023M742850);Innovation Foundation for Doctor Dissertation of Northwestern Polytechnical University(No.CX2021025)。

摘　　要：This study presents a low-noise,high-rate front-end readout application-specific integrated circuit(ASIC)designed for the electromagnetic calorimeter(ECAL)of the Super Tau-Charm Facility(STCF).To address the high background-count rate in the STCF ECAL,the temporal features of signals are analyzed node-by-node along the chain of the analog front-end circuit.Then,the system is optimized to mitigate the pile-up effects and elevate the count rate to megahertz levels.First,a charge-sensitive amplifier(CSA)with a fast reset path is developed,enabling quick resetting when the output reaches the maximum amplitude.This prevents the CSA from entering a pulse-dead zone owing to amplifier saturation caused by the pile-up.Second,a high-order shaper with baseline holder circuits is improved to enhance the anti-pile-up capability while maintaining an effective noise-filtering performance.Third,a high-speed peak-detection and hold circuit with an asynchronous first-input-first-output buffer function is proposed to hold and read the piled-up signals of the shaper.The ASIC is designed and manufactured using a standard commercial 1P6M 0.18μm mixed-signal CMOS process with a chip area of 2.4 mm×1.6 mm.The measurement results demonstrate a dynamic range of 4–500 fC with a nonlinearity error below 1.5%.For periodically distributed input signals,a count rate of 1.5 MHz/Ch is achieved with a peak time of 360 ns,resulting in an equivalent noise charge(ENC)of 2500 e^(-)-.The maximum count rate is 4 MHz/Ch at a peak time of 120 ns.At a peak time of 1.68μs with a 270 pF external capacitance,the minimum ENC is 1966 e^(-)-,and the noise slope is 3.08 e^(-)-∕pF.The timing resolution is better than 125 ps at an input charge of 200 fC.The power consumption is 35 mW/Ch.

关 键 词：Readout electronics APD Charge measurement High count rate STCF 

分 类 号：TN7[电子电信—电路与系统]