一种高性能PCIe接口设计与实现  

Design and implementation of high⁃performance PCIe interface

作　　者：张梅娟[1] 辛昆鹏 周迁 ZHANG Meijuan;XIN Kunpeng;ZHOU Qian(The 58 Research Institute of China Electronic Technology Group Corporation,Wuxi 214000,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214000

出　　处：《现代电子技术》2025年第8期70-74,共5页Modern Electronics Technique

摘　　要：多款处理器在PCIe 2.0×4下传输速率不足理论带宽的20%,最高仅有380 MB/s,不能满足实际应用需求。为解决嵌入式处理器PCIe接口传输速率过低的问题,设计一款高性能PCIe接口,有效提高了接口数据传输速率。经性能瓶颈系统分析,增加设计PCIe DMA与处理器Cache一致性功能,能解决DMA传输完成后软件Cache同步耗时严重的问题,使速率提升3.8倍,达到1 450 MB/s。在硬件设计上DMA支持链表模式,通过描述符链表将分散的内存集聚起来,一次DMA启动可完成多个非连续地址内存的数据传输,并优化与改进软件驱动中分散集聚DMA实现方式,充分利用硬件Cache一致性功能,进一步提升10%的传输速率,最终达到PCIe 2.0×4理论带宽的80%。此外,该PCIe接口采用多通道DMA的设计,最大支持8路独立DMA读写通道,可应用于多核多任务并行传输数据的应用场景,更进一步提升整体数据传输带宽。经验证,该PCIe接口具有良好的稳定性和高效性,最大可支持8通道数据并行传输,且单通道传输速率可达到理论速率的80%。The transmission rate of multiple processors under PCIe 2.0×4 is less than 20%of the theoretical bandwidth,and the maximum transmission rate is only 380 MB/s,which cannot meet the practical application requirements.In order to solve the problem of low transmission rate of PCIe interface of embedded processor,a high-performance PCIe interface is designed,which effectively improves the data transmission rate of the interface.After analyzing the performance bottleneck system,the consistency functions between PCIe DMA and processor Cache are designed to solve the serious problem of software Cache synchronization time after DMA transfer is completed,and the speed is increased by 3.8 times to 1450 MB/s.In the hardware design,DMA supports the linked list mode,and the scattered memory is aggregated by means of the descriptor linked list.One DMA start can complete the data transmission of multiple non-contiguous address memory,and optimize and improve the decentralized and clustered DMA implementation in the software driver.The hardware Cache consistency function is used to further increase the transmission rate by 10%,reaching 80%of the theoretical bandwidth of PCIe 2.0×4.The PCIe interface is designed with multi-channel DMA,which can support up to 8 independent DMA read and write channels.It can be applied to application scenarios of multi-core and multi-task parallel transmission of data,further improving the overall data transmission bandwidth.It has been verified that the PCIe interface has good stability and efficiency,and can support up to 8-channel data parallelism transmission,and the single-channel transmission rate can reach 80%of the theoretical rate.

关 键 词：PCIe接口 DMA控制器 高速数据传输 CACHE一致性 多通道设计 分散集聚 链表模式 

分 类 号：TN402-34[电子电信—微电子学与固体电子学]