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作 者:Wei Liao Wentao Qian Junyang An Lei Liang Zhiyan Hu Junzhuan Wang Linwei Yu
出 处:《Nano-Micro Letters》2025年第7期42-52,共11页纳微快报(英文版)
基 金:financial support received from the National Key Research Program of China under granted No.92164201;the National Natural Science Foundation of China for Distinguished Young Scholars No.62325403;the Fundamental Research Funds for the Central Universities,and the National Natural Science Foundation of China under No.61934004.
摘 要:Gate-all-around field-effect transistors(GAA-FETs)represent the leading-edge channel architecture for constructing state-of-the-art highperformance FETs.Despite the advantages offered by the GAA configuration,its application to catalytic silicon nanowire(SiNW)channels,known for facile low-temperature fabrication and high yield,has faced challenges primarily due to issues with precise positioning and alignment.In exploring this promising avenue,we employed an in-plane solid–liquidsolid(IPSLS)growth technique to batch-fabricate orderly arrays of ultrathin SiNWs,with diameters of DNW=22.4±2.4 nm and interwire spacing of 90 nm.An in situ channel-releasing technique has been developed to well preserve the geometry integrity of suspended SiNW arrays.By optimizing the source/drain contacts,high-performance GAA-FET devices have been successfully fabricated,based on these catalytic SiNW channels for the first time,yielding a high on/off current ratio of 107 and a steep subthreshold swing of 66 mV dec−1,closing the performance gap between the catalytic SiNW-FETs and state-ofthe-art GAA-FETs fabricated by using advanced top-down EBL and EUV lithography.These results indicate that catalytic IPSLS SiNWs can also serve as the ideal 1D channels for scalable fabrication of high-performance GAA-FETs,well suited for monolithic 3D integrations.
关 键 词:In-plane solid-liquid-solid Ultrathin silicon nanowires Gate-all-around field-effect transistors(GAA-FETs)
分 类 号:TN386[电子电信—物理电子学]
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