一种低杂散低抖动的亚采样锁相环设计  

A low-spurious,low-jitter sub-sampled phase-locked loop

作　　者：杨煜 高海军 王梓任 沈啸伟 YANG Yu;GAO Haijun;WANG Ziren;SHEN Xiaowei(School of Electronics and Information Engineering,Hangzhou Dianzi University,Zhejiang Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学电子信息学院,杭州310018

出　　处：《杭州电子科技大学学报(自然科学版)》2025年第2期67-75,共9页Journal of Hangzhou Dianzi University:Natural Sciences

摘　　要：基于SMIC 55 nm工艺,采样亚采样技术设计了一款低杂散、低抖动的2.4 GHz锁相环。针对传统电荷泵锁相环输出信号抖动较大和带内噪声较高,引入亚采样技术以实现锁相环低抖动性能;研究了亚采样锁相环的参考杂散的三个影响机制,并根据这三种影响机制提出了Dummy采样器、隔离缓冲器和新型亚采样电荷泵的方法,以减小输出信号的参考杂散。为了避免锁频错误和减小锁定时间,提出了一种含有新型死区产生电路的锁频环路。考虑到输入信号对输出噪声的影响,设计了一种占空比可调输入信号缓冲器,进一步减小输出参考杂散。仿真结果表明,在1.2 V电源电压下,该亚采样锁相环在50 MHz频偏处参考杂散为-87.72 dBc,带内相位噪声为-126.3 dBc/Hz@1 MHz,整体的功耗为11.72 mW。Based on the SMIC 55 nm process,a 2.4 GHz phase-locked loop(PLL) with sub-sampling technology was designed to achieve low spurious and low jitter performance.In response to the issues of significant jitter and high in-band noise in traditional charge pump PLLs,the sub-sampling technique was introduced.Additionally,the three mechanisms affecting reference spurs in the sub-sampling PLL were investigated,and methods such as the Dummy sampler,isolation buffer,and a novel sub-sampling charge pump were proposed to reduce the level of reference spurs in the output signal.To avoid frequency locking errors and reduce lock-in time,a frequency locking loop incorporating a novel dead-zone circuit was employed.Considering the influence of the input signal on output noise,a variable duty cycle input signal buffer was designed to further decrease reference spurs.Simulation results demonstrate that under a 1.2 V power supply voltage,the sub-sampling PLL achieves a reference spur level of-87.72 dBc at a 50MHz frequency offset and an in-band phase noise of-126.3 dBc/Hz at 1 MHz.The overall power consumption of the system is 11.72 mW.

关 键 词：亚采样锁相环 Dummy采样器 低杂散 低抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学]