基于ESD和Latch UP的芯片版图设计优化技术  

Optimization technology for chip layout design

作　　者：吴美芳 WU Meifang(Shanghai Taisi Microelectronics Co.,Ltd.,Shanghai 201210,China)

机构地区：[1]上海泰矽微电子有限公司,上海201210

出　　处：《中国高新科技》2025年第4期9-10,16,共3页

摘　　要：基于ESD和Latch UP两种导致芯片失效的主要原因,探究了芯片版图设计优化技术。选择栅极接地NMOS管作为保护器件,通过加大栅极接地NMOS管面积,增加栅端到漏端的距离以及利用Salicide工艺降低栅极电阻和漏极电阻等措施,降低静电泄放电流对芯片的影响。增加NMOS和PMOS间隔距离,添加保护环以及设置独立双阱保护等措施,抑制闩锁形成,实现保护芯片的目的。Based on the two main causes of chip failure,ESD and Latch UP,this paper explores the optimization techniques for chip layout design.Selecting a gate grounded NMOS transistor as a protective device,measures such as increasing the area of the gate grounded NMOS transistor,increasing the distance between the gate and drain terminals,and using Salicide technology to reduce gate and drain resistance are taken to reduce the impact of electrostatic discharge current on the chip.Measures such as increasing the distance between NMOS and PMOS,adding protective rings,and setting up independent double well protection are taken to suppress latch up formation and achieve the purpose of protecting the chip.

关 键 词：芯片版图设计 栅极接地NMOS管 独立双阱保护 

分 类 号：TN40[电子电信—微电子学与固体电子学]