Comparative Analysis of Noise Margin Between Pure SET-SET and Hybrid SET-PMOS Inverters  

作　　者：Fan Zhang Yi Liu Yibo Wang Minghu Wu Sheng Hu Youli Dong 

机构地区：[1]Hubei Key Laboratory for High-Efficiency Utilization of Solar Energy and Operation Control of Energy Storage System,Hubei University of Technology,Wuhan 430068,China [2]School of Electrical and Electronic Engineering,Hubei University of Technology,Wuhan 430068,China

出　　处：《Chinese Journal of Electronics》2025年第1期146-155,共10页电子学报(英文版)

基　　金：supported by the Natural Science Foundation of Hubei Province(Grant No.2022CFA007);the Science and Technology Project of Hubei Province(Grant No.2022BEC017);the Key Research and Development Plan of Hubei Province(Grant No.2021BGD013);the National Natural Science Foundation of China(Grant Nos.11605051 and 11875146)。

摘　　要：Single-electron transistor(SET)is considered as one of the promising candidates for future electronic devices due to its advantages of low power consumption and high integration.The comparative analysis of SET-based inverters,especially the noise margin,is carried out.Pure SET-SET and hybrid SET with p type metal oxide semiconductor(SET-PMOS)inverters are designed for investigation.The effects of SET supply voltage,junction resistance and junction capacitance on noise tolerance and power consumption of inverters are studied.For hybrid SET-PMOS inverters,the noise margin for a logic high(NMH)is less than 60 mV under various conditions,which may become the bottleneck of its application.For pure SET-SET inverters,both NMH and the noise margin for a logic low(NML)could reach 300 mV at a supply voltage of 0.8 V.The minimum power consumption of pure SET-SET and hybrid SET-PMOS inverters is 2.85 nW and 58 nW,respectively.The pure SET-SET inverters have greater noise tolerance and lower power consumption,which is more conducive to large-scale integration.When junction capacitance C_(J)=0.0273 aF and junction resistance R_(T)≥1 MΩin SET-SET inverters at a supply voltage of 0.8 V,the NMH and NML are not significantly affected by the junction resistance and the noise margin fluctuates at 300 mV.

关 键 词：Pure SET-SET Hybrid SET-PMOS Noise tolerance Power consumption 

分 类 号：TN386[电子电信—物理电子学]