一种基于反相器放大器的低功耗10 bit 40 MS/s流水线ADC  

A low power 10 bit 40 MS/s pipelined analog-to-digital converter based on inverter-based amplifier

作　　者：杨艳军 陈鸣 黄成强 YANG Yanjun;CHEN Ming;HUANG Chengqiang(School of Physics and Electronic Science,Zunyi Normal College,Zunyi 563006,China;Institute of Microelectronics of Chinese Academy of Science,Beijing 100029,China)

机构地区：[1]遵义师范学院物理与电子科学学院,贵州遵义563006 [2]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2025年第4期124-130,共7页Microelectronics & Computer

基　　金：国家自然科学基金(62164014);贵州省科技厅基础研究计划(黔科合基础-ZK[2021]一般330);遵义市科技计划(遵市科合HZ字(2024)141号)。

摘　　要：提出了一种基于反相器的低功耗全差分运算放大器,通过引入正反馈提高放大器的增益和速度。利用设计的全差分运算放大器和相关电平位移技术,基于180 nm CMOS工艺设计了一款低功耗10 bit 40 MS/s流水线模数转换器(Analog-to-Digital Converter,ADC)。后仿真结果表明,在1.8 V电源电压下,ADC功耗为5.45 mW;当输入信号的频率为1.99707 MHz时,ADC的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)为73.2 dB,信号噪声失真比(Signal to Noise and Distortion Ratio,SNDR)为60.8 dB,有效位数(Effective Number Of Bits,ENOB)为9.8位,最大微分非线性(Differential Nonlinearity,DNL)为+0.38 LSB,最大积分非线性(Integral Nonlinearity,INL)为−0.48 LSB。A low power fully differential operational amplifier based on inverter is proposed.The gain and speed of the amplifier are improved by introducing positive feedback.By using the designed fully differential op-amp and the correlated level shifting technique,a low-power 10 bit 40 MS/s pipelined Analog-to-Digital Converter(ADC)is designed based on 180 nm CMOS process.The post-simulation results show that the power consumption of the ADC is 5.45 mW at a supply voltage of 3.3 V.When the frequency of the input signal is 1.99707 MHz,the ADC has a Spurious-Free Dynamic Range(SFDR)of 73.2 dB,a signal to noise and distortion ratio(SNDR)of 60.8 dB,an Effective Number Of Bits(ENOB)of 9.8 bit,a maximum Differential Nonlinearity(DNL)of+0.38 LSB,and a maximum Integral Nonlinearity(INL)of−0.48 LSB.

关 键 词：反相器 全差分放大器 相关电平位移 流水线ADC 

分 类 号：TN432[电子电信—微电子学与固体电子学]