基于FPGA的高速AES实现与列混合改进  

Implementation of high-speed AES based on FPGA and improvement of MixColumn

作　　者：申锦尚 张庆顺[1,2] 宋铁锐 SHEN Jinshang;ZHANG Qingshun;SONG Tierui(College of Electronic and Information Engineering,Hebei University,Baoding 071000;Machine Vision Technology Innovation Center of Hebei Province,Baoding 071000,China)

机构地区：[1]河北大学电子信息工程学院,河北保定071000 [2]河北省机器视觉技术创新中心,河北保定071000

出　　处：《计算机工程与科学》2025年第4期612-620,共9页Computer Engineering & Science

基　　金：河北大学科研创新团队支撑项目(IT2023B05)。

摘　　要：提出了一种基于FPGA的AES高速通信实现方案。通过将加密过程拆分为30级并行流水线结构,提高了通信速度和加密效率。同时,根据AES中列混合部分特殊的GF(28)有限域运算规则和FPGA并行运算的结构特点,设计了中间量交叉列混合结构。该结构可以有效地减少列混合与逆列混合部分的运算延迟和使用面积,提高了加密效率。从逻辑代数的角度,分析了传统列混合结构、较新的列混合结构和中间量交叉计算结构之间计算资源使用量的不同。最终在Xilinx公司的XC5VSX240T芯片上进行了验证,验证结果表明,此方案实现了吞吐量为60.928 Gbps和加密效率为14.875 Mbps/LUT的性能。A high-speed communication implementation scheme for AES based on FPGA is proposed.By splitting the encryption process into a 30-level parallel pipeline structure,communication speed and encryption efficiency can be improved.At the same time,based on the special GF(28)finite field operation rules of the MixColumn parts in AES and the structural characteristics of FPGA parallel operation,an intermediate cross-MixColumn structure is designed.This structure can effectively reduce the computational delay and usage area of MixColumn and inverse MixColumn parts,and improve the encryption efficiency.From the perspective of logical algebra,the differences in computational resource usage between traditional MixColumn structures,newer MixColumn structures,and inter-mediate cross computing structures are analyzed.Finally,the verification results on Xilinx’s XC5VSX240T chip show that the proposed scheme achieves a throughput of 60.928 Gbps and an encryption efficiency of 14.875 Mbps/LUT.

关 键 词：FPGA AES加密算法 列混合 流水线 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]