An 85 mm×89 mm 64M pixel high-speed CMOS image sensor with a negative capacitance circuit  

作　　者：Ruiming XU Zhongjie GUO Suiyang LIU Ningmei YU Yuan YANG Longsheng WU 

机构地区：[1]Department of Electronics,Xi’an University of Technology,Xi’an 710048,China [2]School of Microelectronics,Xidian University,Xi’an 710071,China

出　　处：《Science China(Information Sciences)》2025年第4期393-394,共2页中国科学(信息科学)(英文版)

基　　金：supported in part by National Natural Science Foundation of China(Grant No.62171367);Shaanxi Innovation Capability Support Project(Grant No.2022TD-39)。

摘　　要：CMOS image sensors(CIS)have supplanted charge-coupled devices as the dominant technology for consumer imaging applications because of their high integration,low power consumption,and affordability.As CMOS image sensor technology continues to advance,the demand for higher resolutions and faster frame rates increases.To achieve faster frame rates,large array CIS must be capable of reading image signals at high speeds.The current dominant architecture for CIS is column-parallel.As the array size expands,the column bus may extend to tens or even hundreds of millimeters,leading to a significant increase in parasitic effects.As a result,the frame rate is limited by the establishment time of the column bus signal.

关 键 词：high speed cmos image sensors low power consumption cmos image sensors cis high integration cmos image sensor charge coupled devices reading image signals negative capacitance cis 

分 类 号：TN386.5[电子电信—物理电子学]