锁相环中差分环形压控振荡器的性能设计与研究  

Performance Design and Research of Differential Loop Voltage Controlled Oscillators in Phase Locked Loops

作　　者：郭升伟 柴一峰 王炳林 谭圣霞 朱中华[1] GUO Shengwei;CHAI Yifeng;WANG Binglin;TAN Shengxia;ZHU Zhonghua

机构地区：[1]湖南科技大学,湖南湘潭411201

出　　处：《电力系统装备》2025年第2期25-27,共3页Electric Power System Equipment

摘　　要：基于TSMC180nm BCD CMOS工艺设计了一种差分环形压控振荡器。电路采用三级延时单元环形结构作为核心,结合Maneatis对称负载,显著提升了延时单元的线性度、对称性及稳定性。此外,设计中集成了偏置电路和缓冲电路,偏置电路的设计关键在于提升输出阻抗,通过优化尾电流源来实现,从而加强电路稳定性与抗干扰性。缓冲电路则实现了0~1.8V电压输出,确保信号占空比接近50%,并增强了驱动能力以适应后续并转串模块的需求。使用Cadence Spectre在1.8V电源电压下的模拟仿真结果显示,该VCO具备180~795MHz的宽频率调节范围,在1MHz频偏处相位噪声达到–92.7534dBc/Hz,在典型工作频率600MHz时输出抖动低于1ps。这些性能指标表明,VCO具有更好的稳定性和噪声性能,适合高精度锁相环。A differential ring voltage controlled oscillator was designed based on TSMC180 nm BCD CMOS technology.The circuit adopts a three-stage delay unit ring structure as the core,combined with Maneitis symmetric load,significantly improving the linearity,symmetry,and stability of the delay unit.In addition,bias circuits and buffer circuits are integrated in the design.The key to designing the bias circuit is to improve the output impedance by optimizing the tail current source,thereby enhancing the stability and anti-interference ability of the circuit.The buffer circuit achieves a voltage output of 0 V to 1.8 V,ensuring a signal duty cycle close to 50%and enhancing driving capability to meet the needs of subsequent parallel to serial modules.The simulation results using Cadence Spectre at a power supply voltage of 1.8 V show that the VCO has a wide frequency adjustment range of 180 MHz to 795 MHz,with phase noise reaching-92.7534 dB/Hz at a frequency offset of 1 MHz,and output jitter of less than 1 ps at a typical operating frequency of 600 MHz.These performance indicators indicate that VCO has better stability and noise performance,making it suitable for high-precision phase-locked loops.

关 键 词：环形压控振荡器 锁相环 延时单元 偏置电路 

分 类 号：TN752[电子电信—电路与系统]