FireLink:一种面向芯粒设计空间探索的评估框架  

FireLink:An Evaluation Framework for Chiplet Design Space Exploration

作　　者：李开 曾坤[1,2] 荣培涛[1,2] 陈志强 张甜 王永文 Li Kai;Zeng Kun;Rong Peitao;Chen Zhiqiang;Zhang Tian;Wang Yongwen(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Key Laboratory of Advanced Microprocessor Chips and Systems(National University of Defense Technology),Changsha 410073)

机构地区：[1]国防科技大学计算机学院,长沙410073 [2]先进微处理器芯片与系统重点实验室(国防科技大学),长沙410073

出　　处：《计算机研究与发展》2025年第5期1108-1122,共15页Journal of Computer Research and Development

基　　金：高层次科技创新人才工程人选自主科研项目(22-TDRCJH-02-006);国家自然科学基金青年科学基金项目(NSFC-62202481);国防科技大学科研计划项目(ZK22-05)。

摘　　要：基于先进封装技术的芯粒(Chiplet)集成芯片在制造成本、设计效率以及专用定制等方面更具优势,是延续芯片性能增长的有效途径.设计空间探索(design space exploration,DSE)作为体系结构量化分析的重要方法,能够帮助设计者理解并权衡设计参数间的复杂关系.但是将传统的芯片体系结构DSE方法直接应用于Chiplet设计时,存在评估不全面、模拟不精确以及探索效率低下等问题,针对这些问题提出了解决方案FireLink,作为一个面向Chiplet设计空间探索的评估框架,它支持Chiplet微架构以及互连网络的建模和模拟,具备高效评估性能、功耗、面积和成本指标的能力.此外,在该框架下采用了ID3(iterative dichotomiser 3)机器学习算法进行了实验,结果显示该框架能够有效提高DSE的效率.与现有的DSE框架和方法相比,FireLink在评估全面性、建模完整性和高效性方面具有显著优势,使得设计者能够在更短时间内探索更广泛的设计空间,进而选定较优的Chiplet设计方案.The Chiplet-integrated chip based on advanced packaging technology offers a number of advantages in terms of manufacturing cost,design efficiency and special customization,etc.We represent a new and effective method of maintaining the performance growth of the chip in the post-Moore era.As an important method of quantitative analysis of architectural design,design space exploration(DSE)can assist designers in comprehending and evaluating the intricate interrelationships between design parameters.However,when applying the traditional DSE method directly to the Chiplet design,it gives rise to issues such as incomplete evaluation,inaccurate simulation,and low efficiency.The solution to these problems is FireLink,an evaluation framework for Chiplet design space exploration.FireLink supports the modelling and simulation of Chiplet microarchitectures and interconnection networks,and is capable of efficiently evaluating performance,power,area and cost metrics.Furthermore,experiments are conducted using ID3(iterative dichotomiser 3)machine learning algorithm in this framework,which has been demonstrated to effectively improve the efficiency of DSE.In comparison with existing DSE methodologies,FireLink exhibits notable advantages in comprehensiveness of evaluating,completeness of modeling and efficiency of DSE,therefore designers can explore a wider range of design space in a shorter time,so as to select a better Chiplet design scheme.

关 键 词：芯粒 设计空间探索 模拟 评估 微架构 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]