一种低功耗降压型DC-DC转换器设计  

A Low‑power Step‑down DC‑DC Converter Design

作　　者：宋阜恒 蔡甜甜 王培浩 王紫阳 夏晓娟[1] SONG Fuheng;CAI Tiantian;WANG Peihao;WANG Ziyang;XIA Xiaojuan(College of Integrated Circuit Science and Engineering(College of Industry?Education Integration),Nanjing Post and Communications University,Nanjing,210023,CHN)

机构地区：[1]南京邮电大学集成电路科学与工程学院(产教融合学院),南京210023

出　　处：《固体电子学研究与进展》2025年第2期79-85,共7页Research & Progress of SSE

基　　金：航空科学基金资助项目(202200240X9001)。

摘　　要：设计了一种超低静态功耗的同步整流降压型脉冲频率调制模式的DC-DC转换器。在轻载条件下,利用输出电压启动电路,降低静态功耗,并加入电感峰值限流,减小输出电压纹波。基于0.5μm的CMOS工艺进行设计以及仿真验证,测试结果表明,当输出电压为1.8 V时,该芯片的静态电流仅为760 nA。全负载效率在90%以上,最高效率可以达到93.12%。An ultra-low static power consumption synchronous rectifier buck pulse frequency modulation(PFM)mode DC-DC converter was designed.The output voltage startup circuit was utilized to reduce the static power consumption under light load conditions and inductive peak current limiting was added to reduce the output voltage ripple.Based on the 0.5μm CMOS process for design as well as simulation verification,the test results show that the chip's quiescent current is only 760 nA when the output voltage is 1.8 V.The full-load efficiency is above 90%,and the maximum efficiency can reach 93.12%.

关 键 词：降压型DC-DC转换器 低功耗 高效率 脉冲频率调制模式 

分 类 号：TN432[电子电信—微电子学与固体电子学]