基于低功耗FPGA芯片的数字控制电路设计  

Design of Digital Control Circuits Based on FPGA Chips with Low Power Consumption

作　　者：徐亚维 韩博玺 邓强 XU Yawei;HAN Boxi;DENG Qiang(Sichuan Institute of Aerospace Electronic Equipment,Chengdu 610100,China)

机构地区：[1]四川航天电子设备研究所,四川成都610100

出　　处：《现代信息科技》2025年第8期29-33,共5页Modern Information Technology

摘　　要：数字控制电路是雷达接收机系统的组成之一。同等功能设计下,为降低数字控制电路核心器件FPGA全温范围内的功耗,优化数字控制电路的设计,将国产FPGA器件JFM7K325T和JFMK50T4进行同比设计,可得JFM7K325T常温功耗约为2.3 W,全温范围(-40~+60 ℃)内会功耗达到1.9~8.0 W,内核电压所需电流最大为2 A;JFMK50T4常温功耗仅1.175 W,全温范围内功耗最大达到2.8 W,同等环境温度下,功耗降低了1/2~3/4,大幅降低芯片的供电设计、热设计、空间设计等,单只芯片成本也可降低2/3。Digital control circuits constitute one of the components of the radar receiver system.Under the same functional design,in order to reduce the power consumption of the core device FPGA of the digital control circuit within the full temperature range,the design of the digital control circuit is optimized.Comparative designs are conducted for domestic FPGA devices JFM7K325T and JFMK50T4.It can be obtained that the power consumption of JFM7K325T at normal temperature is approximately 2.3 W,and within the full temperature range(-40 to+60℃),the power consumption reaches 1.9 to 8 W,and the maximum current required by the core voltage is 2 A.The power consumption of JFMK50T4 at room temperature is only 1.175 W,and the maximum power consumption reaches 2.8 W within the full temperature range.Under the same environmental temperature,the power consumption is decreased by 1/2 to 3/4.The power supply design,thermal design,and spatial design of the chips are significantly reduced,and the cost of a single chip can also be lowered by 2/3.

关 键 词：国产化 FPGA 低功耗 数字控制电路 

分 类 号：TN711[电子电信—电路与系统] TN713