基于可变编码块流水的可重构HEVC帧内环路设计  

DESIGN OF RECONFIGURABLE HEVC INTRA-LOOP BASED ON VARIABLE CODING BLOCK PIPELINE

作　　者：夏馨缘 山蕊 崔馨月 杨坤 廖望 Xia Xinyuan;Shan Rui;Cui Xinyue;Yang Kun;Liao Wang(School of Electronic Engineering,Xi’an University of Posts&Telecommunications,Xi’an 710121,Shaanxi,China;College of Safety Science and Engineering,Xi’an University of Science and Technology,Xi’an 710054,Shaanxi,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安科技大学安全科学与工程学院,陕西710054

出　　处：《计算机应用与软件》2025年第4期107-113,165,共8页Computer Applications and Software

基　　金：国家自然科学基金项目(61802304,61834005,61772417,61602377,61634004)。

摘　　要：高效视频编码标准(HEVC)硬件实现过程中,其高计算复杂度和高数据依赖性不仅阻碍了视频实时编码的性能,也带来了更高的资源消耗。通过分析帧内环路各个算法之间处理像素块时产生的数据/时序依赖关系,基于可变编码块流水的HEVC帧内环路可重构阵列结构,各模块间采用邻接互连接口完成握手通信,实现整个帧内环路编码块之间流水处理,提高帧内环路的计算效率。实验结果表明,所提方法在满足计算速度与硬件资源要求的同时,与基于串行的帧内环路编码处理电路相比,执行时间减少了87%,时钟频率达125 MHz。During the hardware implementation of the high efficiency video coding standard(HEVC),its high computational complexity and high data dependence not only hinder the performance of real-time video encoding,but also bring higher resource consumption.In this paper,we analyzed the data/timing dependency relationship between the various algorithms of the intra-frame loop when processing pixel blocks,and the HEVC intra-loop reconfigurable array structure based on the variable coding block pipeline is completed.By using the adjacent interconnection interface between the modules,the handshake communication realized the pipeline processing between the entire intra-frame loop coding blocks,and improved the calculation efficiency of the intra-frame loop.The experimental results show that the proposed method meets the requirements of computing speed and hardware resources.Compared with the serial-based intra-loop encoding processing circuit,the execution time is reduced by 87%,and the clock frequency reaches 125 MHz.

关 键 词：可变编码块流水 可重构阵列处理器 高效视频编码 帧内环路 邻接互连 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]