基于查找表均衡的高速SerDes发送端设计  

Design of a Lookup Table Equalized High-Speed SerDes Transmitter

作　　者：陶保明 张春茗 任一凡 小亮 Tao Baoming;Zhang Chunming;Ren Yifan;Ji Xiaoliang(School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《半导体技术》2025年第5期488-496,共9页Semiconductor Technology

摘　　要：为使高速串行器/解串器(SerDes)发送端具有更大的均衡灵活性,采用UMC 28nm CMOS工艺设计了一种基于数字信号处理(DSP)-数模转换器(DAC)结构的高速SerDes发送端。通过将发送端中前馈均衡功能以查找表(LUT)形式集成至DSP中,灵活解决了信道高频损耗严重和信号完整性问题,并简化了全定制电路设计的复杂度;其主体结构包括DSP、温度编码器、重定时器、32:4多路复用器(MUX)、1 UI脉冲发生器+4:1 MUX、源串联端接(SST)型DAC驱动器。仿真结果显示:在1.05 V工作电压且信道衰减为12 dB@16 GHz条件下,发送端输出32 Gbit/s NRZ信号眼高为258 mV,眼宽为0.75UI;输出64 Gbit/s PAM4信号眼高为64 mV,眼宽为0.40 UI;版图面积为0.116 mm^(2),电路功耗为57.42 mW,获得了良好的均衡性能。To achieve greater flexibility in equalization for the transmitter of a high-speed serializer/deserializer(SerDes),a high-speed SerDes transmitter based on a digital signal processing(DSP)-digital-to-analog converter(DAC)architecture was designed using UMC 28 nm CMOS process.By integrating the feed-forward equalization(FFE)function into the DSP in the form of a lookup table(LUT),the design flexibly addresses severe high-frequency channel loss and signal integrity issue while simplifying the complexity of full-custom circuit design.The main structure includes a DSP,thermal encoder,re timer,32:4 multiplexer(MUX),1-unit interval(UI)pulse generator combined with a4:1 MUX and a source-series terminated(SST)DAC driver.Simulation results show that under a1.05 V operation voltage and 12 dB@16 GHz channel attenuation,the transmitter outputs 32 Gbit/s NRZ signals with an eye height of 258 mV and eye width of 0.75 UI,along with 64 Gbit/s PAM4 signals with an eye height of 64 mV and eye width of 0.40 UI.The layout area is 0.116 mm^(2) with a power consumption of 57.42 mW,indicating good equalization performance.

关 键 词：数字信号处理(DSP) 前馈均衡 串行器/解串器(SerDes) 源串联端接(SST)驱动器 数模转换器(DAC) 

分 类 号：TN79[电子电信—电路与系统] TN432