片间互连总线协议层关键技术研究  

Research on key technology of inter-chip interconnection protocol layer

作　　者：邢世远 张见齐 王焕东 吴学智 吴瑞阳 XING Shiyuan;ZHANG Jianqi;WANG Huandong;WU Xuezhi;WU Ruiyang(Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049;Loongson Technology Corporation Limited,Beijing 100095;State Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190)

机构地区：[1]中国科学院计算技术研究所,北京100190 [2]中国科学院大学,北京100049 [3]龙芯中科技术股份有限公司,北京100095 [4]处理器芯片全国重点实验室(中国科学院计算技术研究所),北京100190

出　　处：《高技术通讯》2025年第2期113-123,共11页Chinese High Technology Letters

基　　金：中国科学院战略性先导科技专项(C类)课题(XDC05020100)资助项目。

摘　　要：随着以数据分析、网络搜索和虚拟现实为核心的新数据中心和高性能计算应用程序的开发,高性能计算平台上需要传输的数据量不断增加,数据密集型应用对片间数据传输带宽需求的增长从未停止,片间互连总线被视为系统瓶颈的潜在来源。相比于在物理层提高总线传输速率和增加信号数量提升带宽的传统做法,在总线协议层通过结构设计优化提高带宽利用率也是提升总带宽的重要解决思路。相比前者,后者不会引入额外成本开销,并且具有能耗友好的优势。本文在协议层提出了3个关键技术,分别是数据命令分离的片内语义到跨片语义转换方案、基于年龄(Age)策略的仲裁算法和片间数据压缩技术。数据命令分离的语义策略具有很强的跨架构通用性,是仲裁和压缩的前提。片间总线协议层仲裁和压缩技术通过结构的方法大幅提高了总线带宽利用率。在Synopsys Zebu仿真加速平台上的实验结果表明,本文方法的总线架构在关闭和开启数据压缩情形下带宽利用率分别为45.8%和69.7%,达到国际先进水平。With the development of new data centers and high-performance computing applications centered around data analytics,web searching,and virtual reality,the demand for data movement on high-performance computing plat-forms has been continuously increasing.The growth in bandwidth requirements for inter-chip data transfers by data-intensive applications remains unabated,with interconnect buses being perceived as potential sources of system bot-tlenecks.In contrast to traditional approaches of enhancing bandwidth by increasing transmission rates and adding signal counts at the physical layer,optimizing bandwidth utilization through architecture design at the bus protocol layer is also an important approach to increasing overall bandwidth.Compared with the former,the latter does not incur additional cost overheads and offers energy-efficient advantages.This paper proposes three key technologies at the protocol layer,namely,the intra-chip semantic to inter-chip semantic conversion scheme with data-command separation,arbitration algorithm based on the Age strategy,and inter-chip data compression technology.The data-command separation semantic strategy exhibits strong cross-architecture generality and serves as a prerequisite for arbitration and compression.The arbitration and compression technologies at the inter-chip bus protocol layer signif-icantly enhance bus bandwidth utilization through architecture methods.Experimental results obtained on the Syn-opsys Zebu emulation acceleration platform demonstrate that the bus architecture employing the proposed methods achieves bandwidth utilization of 45.8%and 69.7%respectively under conditions of data compression disabled/enabled,reaching the international advanced level.

关 键 词：片间互连 总线协议层 语义转换 仲裁 数据压缩 仿真加速器 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]