基于FPGA的全数字锁相环分析与设计  

Analysis and Design of All-digital Phase-locked Loop Based on FPGA

作　　者：马莽原 杨雨佳 邹胜福 石利颖 封俊宝 Ma Mangyuan;Yang Yujia;Zou Shengfu;Shi Liying;Feng Junbao(Nanyang Vocational College,Nanyang,Henan 474500,China)

机构地区：[1]南阳职业学院,河南南阳474500

出　　处：《黑龙江科学》2025年第8期162-164,共3页Heilongjiang Science

基　　金：2024-2025年南阳市科技攻关计划项目“直线电机成型线圈的对地绝缘包扎关键技术”(2024KJGG0301)。

摘　　要：感应加热电源采用的模拟锁相环与数模混合锁相环在超高频阶段易受干扰,影响电源工作的稳定性。针对这一问题,设计一种基于FPGA的全数字锁相环,采用离散系统Z域法分析其工作原理,通过Xilinx ISim进行仿真验证,结果表明锁相环设计正确,具有结构简单、稳定性高、锁相范围宽与动态响应快的特点,可为感应加热电源锁相环的全数字化提供新的参考。The analog signal phase-locked loop(PLL)and the mixed-signal PLL,which are susceptible to interference in the ultra-high frequency range.It can affect the stability of induction heating power supplies.In order to solve this problem,a Flip-flop type all-digital phase-locked loop(ADPLL)based on Field Programmable Gate Array(FPGA)is designed.The working principle of this all-digital phase-locked loop is analyzed by the discrete-time system Z-domain method,and is verified through simulation with Xilinx ISim.The results demonstrate that the design of the all-digital phase-locked loop is correct,with a wide phase-locked range,fast dynamic response,high stability,and a simple structure.It also provides new reference for the full digitalization of phase-locked loops in induction heating power supplies.

关 键 词：感应加热电源 全数字锁相环 FPGA Z域分析 

分 类 号：TM46[电气工程—电器]