一种新型的高性能CPU时钟树自适应优化策略  

A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees

作　　者：樊凌雁[1] 张哲 黄灿坤 骆建平 刘海銮 FAN Lingyan;ZHANG Zhe;HUANG Cankun;LUO Jianping;LIU Hailuan(Microelectronics Research Institute,Hangzhou Dianzi University,Hangzhou 310018,China;Shanghai ESWIN Computing Technology Co.,Ltd.Shanghai 200131,China)

机构地区：[1]杭州电子科技大学微电子研究院,杭州310018 [2]上海奕斯伟计算技术有限公司,上海200131

出　　处：《电子与信息学报》2025年第4期1192-1201,共10页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(U22A2071);科技部重大攻关项目(GG20210104)。

摘　　要：该文基于精简指令集系统(RISC-V)架构提出了一种新型的自适应全流程(ADFF)时钟树优化方法,高效利用有用偏差(useful skew)来优化高性能CPU时钟树,以满足市场对芯片高性能和低功耗的双重需求。针对时钟树,通过选择关键路径并结合理论延迟和缓冲器制造有用偏差,采用循环迭代的方式,在不同流程自适应修复常规流程无法解决的建立时间违例(setup violation)和保持时间违例(hold violation)。为了在提升性能的同时,最大限度降低功耗,该文对加入的延迟单元进行合并(merge)处理,实现功耗与时序的联合优化。最后采用RISC_V CPU核进行验证,研究结果表明,在确保合理功耗的基础上,所提方法显著改善了时序情况,总时序裕量违例几乎完全消除。Objective With continuous advancements in Integrated Circuit(IC)process technology,chip integration levels have steadily increased,driving higher market demands for performance.In the era of intelligence and digitalization,an inherent challenge arises:as the number of logic gates increases,both main frequency and power consumption rise,imposing stricter requirements on digital IC designers.Although existing Electronic Design Automation(EDA)tools optimize timing using useful skew in clock trees,this technique has notable limitations.To address this issue,a novel adaptive full-flow clock tree timing violation correction method is proposed.This method corrects timing violations unresolved by conventional flows while reducing power consumption and improving performance,meeting the market’s dual demands for high-performance and lowpower chips.Methods The ADaptive Full Flow(ADFF)clock tree optimization method is based on the RISC-V CPU architecture.As an open-source architecture,RISC-V offers openness and flexibility,making it widely used in high-performance,low-power processor design.The method exploits imbalances in key path logic depth to enhance optimization.Useful skew is introduced to adjust logic delay distribution,improving overall performance.Timing feedback is incorporated at multiple stages,ultimately forming a joint optimization strategy for power consumption and timing,which enhances clock tree quality and reduces chip load.The method integrates feedback optimization during both the Clock Tree Synthesis(CTS)and routing stages.In the CTS stage,timing paths are traversed to gather feedback,which is then returned to the pre-CTS stage for early intervention.Adaptive iteration accurately identifies critical paths and resolves setup time violations.In the routing stage,targeted strategies address hold time violations,and the merging method reduces power consumption while optimizing timing correction.This enables full-flow correction of clock tree timing violations while improving power efficiency.Results and D

关 键 词：时钟树 有用偏差 自适应 时间违例 联合优化 

分 类 号：TN4[电子电信—微电子学与固体电子学] TN431.2